ASTRA: Automatic Sizing of Transistors with Reasoning Agents

Advancing technology nodes have significantly increased the complexity of transistor sizing in analog circuit design. Although artificial intelligence (AI) techniques show potential, their lack of integrated domain expertise often leads to slow convergence in practical applications. We propose ASTRA (Automatic Sizing of Transistors with Reasoning Agents), a novel optimization framework that implements the Model Context Protocol (MCP) to create structured reasoning pathways between Large Language Models (LLMs), domain knowledge bases, and Bayesian Optimization (BO). ASTRA introduces a two-stage process: first, MCP-guided design initialization that leverages Retrieval-Augmented Generation (RAG) to quickly identify feasible regions using gm/ID methodology; and second, BO-based optimization focused on critical transistors, identified through LLM reasoning with data-driven validation. A key innovation of ASTRA is its ability to seamlessly integrate with and enhance virtually any existing transistor sizing algorithm at minimal additional cost. Unlike purely data-driven or black-box LLM approaches, ASTRA maintains traceable decision processes that can be verified and refined. Evaluated on three real-world analog circuits, ASTRA enhances multiple classical optimization methods, achieving up to 4.35× fewer simulation iterations and 2.36× performance improvements, demonstrating its effectiveness as a general open-source framework for advancing analog circuit sizing.