Approximate Redundant Booth Multiplier Based on Error Compensation Mechanism

In this paper, a novel approximate encoding method is proposed to improve the energy efficiency and reduce the hardware complexity of redundant binary (RB) Booth multipliers. The proposed approximate redundant Booth multiplier (ARBM) realizes an approximation and compensation mechanism by modifying Booth digit set. Therefore, higher-weight error can be compensated by the compensation segment to realize both high approximation bit-width and high accuracy. The proposed multiplier is synthesized using standard 28-nm CMOS process. Compared with traditional Booth multiplier, the implemented result achieves 48%, 22% and 42% reduction in area, delay and power with accuracy loss of 0.195% mean relative error distance (MRED). Compared with state-of-the-art designs, the proposed multiplier shows a significant power reduction and better accuracy-energy trade-off.