TY - GEN
T1 - Approximate computing in MOS/spintronic non-volatile full-adder
AU - Cai, Hao
AU - Wang, You
AU - Naviner, Lirida A.B.
AU - Wang, Zhaohao
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2016 ACM.
PY - 2016/9/14
Y1 - 2016/9/14
N2 - Approximate computing and its related topics have shown the potential in next generation computing systems. In this paper, new circuit level design for approximate computing is proposed based on non-volatile (NV) logic-in-memory structure. Two types of NV approximate adders are implemented with circuit reconfiguration and insufficient writing current. Spin torque transfer magnetic tunnel junction (STT-MTJ) is used as NV memory element in magnetic full adder (MFA). The proposed approximate MFAs are implemented with 28nm ultra thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. Simulation results are presented including power consumption, circuit latency, leakage power, error distance and reliability performance. Low Vdd design strategies are discussed as well.
AB - Approximate computing and its related topics have shown the potential in next generation computing systems. In this paper, new circuit level design for approximate computing is proposed based on non-volatile (NV) logic-in-memory structure. Two types of NV approximate adders are implemented with circuit reconfiguration and insufficient writing current. Spin torque transfer magnetic tunnel junction (STT-MTJ) is used as NV memory element in magnetic full adder (MFA). The proposed approximate MFAs are implemented with 28nm ultra thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. Simulation results are presented including power consumption, circuit latency, leakage power, error distance and reliability performance. Low Vdd design strategies are discussed as well.
KW - Approximate computing
KW - magnetic tunnel junction
KW - nonvolatile full adder
KW - ultra low power
KW - UTBB-FDSOI
UR - https://www.scopus.com/pages/publications/84992079900
U2 - 10.1145/2950067.2950101
DO - 10.1145/2950067.2950101
M3 - 会议稿件
AN - SCOPUS:84992079900
T3 - Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
SP - 203
EP - 208
BT - Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
PB - Presses Polytechniques Et Universitaires Romandes
T2 - 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
Y2 - 18 July 2016 through 20 July 2016
ER -