@inproceedings{9b9c3ef637f44c708b00f04f96694713,
title = "Analytical study of complementary memristive synchronous logic gates",
abstract = "This paper describes an analytical study of synchronous logic gate design based on hybrid structure with MOS and resistive switching non-volatile memories (RS-NVMs). This type of structure allows ultra-low power consumption during power down, while often-used data are saved in RS-NVM cells. The parallel data sensing achieves low-power and fast computation time. The logic gate construction theory, from Boolean equation to hybrid MOS/RS-NVM tree, is deeply detailed. Read and write design guideline, regarding RS-NVM and MOS resistance balance are investigated. Practical implementation is given through transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the concept by using CMOS 40 nm design kit and memory compact models.",
keywords = "Low-Power design, Resistive Switching, complementary cell, synchronous logic gate",
author = "Portal, \{J. M.\} and M. Moreau and M. Bocquet and H. Aziza and D. Deleruyelle and C. Muller and Y. Zhang and E. Deng and Klein, \{J. O.\} and D. Querlioz and D. Ravelosona and C. Chappert and Zhao, \{W. S.\}",
year = "2013",
doi = "10.1109/NanoArch.2013.6623047",
language = "英语",
isbn = "9781479908738",
series = "Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013",
pages = "70--75",
booktitle = "Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013",
note = "2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013 ; Conference date: 15-07-2013 Through 17-07-2013",
}