TY - GEN
T1 - An optimization method for embarrassingly parallel under MIC architecture
AU - Li, Yunchun
AU - Tian, Xiduo
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/3/8
Y1 - 2016/3/8
N2 - Nowadays, heterogeneous architecture of CPU plus accelerator has become a mainstream in supercomputing. Intel lauched its Xeon Phi coprocessor in this context. It uses Intel's many-core architecture, which greatly improves the single node parallelism. This paper studies the optimization of embarrassingly parallel programs under Intel MIC architecture, to maximize the utilization of CPU and Phi processor, and reduce the running time of parallel programs, by combining the computing power of CPU and Phi. This so-called embarrassingly parallel program often have do all main loops, that is, there are no dependencies between iterations, so they can be fully parallelized. This do all loop exists in many typical parallel programs. We come up with a loop allocation method for do all loops under this CPU/MIC architecture, to satisfy the above performance objectives.
AB - Nowadays, heterogeneous architecture of CPU plus accelerator has become a mainstream in supercomputing. Intel lauched its Xeon Phi coprocessor in this context. It uses Intel's many-core architecture, which greatly improves the single node parallelism. This paper studies the optimization of embarrassingly parallel programs under Intel MIC architecture, to maximize the utilization of CPU and Phi processor, and reduce the running time of parallel programs, by combining the computing power of CPU and Phi. This so-called embarrassingly parallel program often have do all main loops, that is, there are no dependencies between iterations, so they can be fully parallelized. This do all loop exists in many typical parallel programs. We come up with a loop allocation method for do all loops under this CPU/MIC architecture, to satisfy the above performance objectives.
KW - Embarrassingly parallel
KW - Exascale
KW - Intel Xeon Phi
KW - Loop allocation
KW - Many-core
KW - Performance tuning
UR - https://www.scopus.com/pages/publications/84978128399
U2 - 10.1109/DCABES.2015.12
DO - 10.1109/DCABES.2015.12
M3 - 会议稿件
AN - SCOPUS:84978128399
T3 - Proceedings - 14th International Symposium on Distributed Computing and Applications for Business, Engineering and Science, DCABES 2015
SP - 17
EP - 20
BT - Proceedings - 14th International Symposium on Distributed Computing and Applications for Business, Engineering and Science, DCABES 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th International Symposium on Distributed Computing and Applications for Business, Engineering and Science, DCABES 2015
Y2 - 18 August 2015 through 24 August 2015
ER -