An FPGA-Based High-Speed Reconfigurable Accelerator for YOLO

This work proposes an instruction-driven reconfigurable high-speed accelerator architecture. By dynamically loading precompiled instruction sequences, it enables the flexible deployment of detection algorithms and effectively avoids frequent circuit synthesis processes. Integrating streaming dataflow, sliding-window mechanisms, and digital signal processor (DSP) reuse techniques, the proposed design is verified on the Xilinx XC7Z100-2FFG900 FPGA platform with YOLOv5n as the benchmark network. It achieves a low per-frame latency of 25 ms, representing a 2.8× reduction in inference latency compared to the central processing unit (CPU). Meanwhile, the utilization rates of look-up tables (LUTs) and block random-access memory (BRAM) are reduced by 37.5% and 24.5% respectively, significantly enhancing the high-speed processing performance and versatility in resource-constrained hardware environments.