An ARM+FPGA SoC Architecture for Efficient Image Processing Using DDR-Cached DPR

Autonomous embedded systems deployed at the edge require real-time, and adaptive visual perception under strict constraints of power, cost, and physical size. Although static Field Programmable Gate Array (FPGA) accelerators provide high computational performance, their fixed architecture often leads to inflexibility and low resource utilization when handling multiple vision algorithms. To overcome these limitations, this paper proposes an adaptive visual processing architecture on a Zynq System-on-Chip (SoC) that leverages Dynamic Partial Reconfiguration (DPR) to enable dynamic hardware module loading. By designating a reconfigurable partition (RP) within FPGA, mission-specific accelerators such as those for mean filtering, enhancement, and edge detection, can be dynamically loaded on-demand. This "Hardware-on-Demand"approach enables time-division multiplexing of hardware functions, significantly improving resource efficiency and system flexibility. Experimental results demonstrate that, compared to conventional static multi-accelerator implementation, the proposed architecture reduces logic resource consumption by over 50% without compromising performance. Moreover, a DDR-based caching mechanism is introduced to reduce reconfiguration latency by over 93%, thereby enhancing the feasibility of the architecture for power and resource-constrained, real-time autonomous systems.