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An approach to reconfigure a fault-tolerant loop system

  • C. T. Liang
  • , S. K. Chen
  • , W. T. Tsai

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

In this paper we use power graph to represent loop networks and propose a distributed reconfiguration protocol for a class of fault-tolerant loop systems under concurrent fault model. With this protocol, (1) faulty processors which revived before reconfiguration starts can be used to recover faults, (2) the system may tolerate more than k fault as long as feasible spare nodes are reachable, and finally self-stabilizes after reconfiguration, (3) every node, not just some designated nodes, can activate spare nodes nearby and responds to the reconfiguration, (4) faults that occur during the process of reconfiguration, and multiple faults that occur simultaneously are both allowed.

源语言英语
主期刊名Architectures, Software Tools and Other General Issues
编辑David W. Walker, Quentin F. Stout
出版商Institute of Electrical and Electronics Engineers Inc.
845-850
页数6
ISBN(电子版)0818621133, 9780818621130
DOI
出版状态已出版 - 1990
已对外发布
活动5th Distributed Memory Computing Conference, DMCC 1990 - Charleston, 美国
期限: 8 4月 199012 4月 1990

出版系列

姓名Proceedings of the 5th Distributed Memory Computing Conference, DMCC 1990
2

会议

会议5th Distributed Memory Computing Conference, DMCC 1990
国家/地区美国
Charleston
时期8/04/9012/04/90

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