A STT-Assisted SOT MRAM-Based In-Memory Booth Multiplier for Neural Network Applications

Computing-in-memory (CIM) is a promising candidate for highly energy-efficient neural networks, alleviating the well-known bottleneck in Von Neumann architecture. MRAM has garnered significant attention in the CIM field, providing advantages in terms of non-volatility, high speed, and endurance. However, most existing MRAM-CIM primarily support low-precision operations, which poses a challenge in fulfilling the requirements of complex neural network models for high inference accuracy. To resolve this dilemma, an in-memory Booth Multiplier is proposed with the aim of enhancing the energy efficiency of neural networks performing multi-bit multiply-and-accumulate (MAC) operations. The MRAM array stores the multiplicand, while the multiplier is encoded by a Booth encoder into corresponding control signals, which perform negation and shift operations, reducing half of the partial products and accelerating the overall processing. Simulation results demonstrate at least a 17.3% improvement in energy efficiency compared to the previous in-SRAM counterpart in 8-bit multiplication.