TY - GEN
T1 - A spin Hall effect-based multi-level cell for MRAM
AU - Shi, Qian
AU - Wang, Zhaohao
AU - Gao, Yuqian
AU - Chang, Liang
AU - Kang, Wang
AU - Zhang, Youguang
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2016 ACM.
PY - 2016/9/14
Y1 - 2016/9/14
N2 - Multi-level cell (MLC) is an efficient solution to improve the storage density of the MRAM. However, the conventional spin transfer torque-based MLC (STT-MLC) suffers from the performance bottlenecks such as high write energy and complicated two-step operation. In this work, we propose a spin Hall effect-based MLC (SHE-MLC) to overcome these bottlenecks. In the SHE-MLC structure, the write current does not pass the MTJ, which avoids the barrier breakdown and reduces the write energy. Moreover, the written data is only dependent on the direction of the write current, thus the two-step operation is not required. Simulation results demonstrate that, under the same access transistor size, e.g. 600 nm, the proposed SHE-MLC can achieve 55× faster write operation and 58× lower write energy than the conventional STT-MLC.
AB - Multi-level cell (MLC) is an efficient solution to improve the storage density of the MRAM. However, the conventional spin transfer torque-based MLC (STT-MLC) suffers from the performance bottlenecks such as high write energy and complicated two-step operation. In this work, we propose a spin Hall effect-based MLC (SHE-MLC) to overcome these bottlenecks. In the SHE-MLC structure, the write current does not pass the MTJ, which avoids the barrier breakdown and reduces the write energy. Moreover, the written data is only dependent on the direction of the write current, thus the two-step operation is not required. Simulation results demonstrate that, under the same access transistor size, e.g. 600 nm, the proposed SHE-MLC can achieve 55× faster write operation and 58× lower write energy than the conventional STT-MLC.
KW - Magnetoresistive random access memory
KW - Non-volatile
KW - multi-level cell
KW - spin Hall effect
UR - https://www.scopus.com/pages/publications/84992062682
U2 - 10.1145/2950067.2950104
DO - 10.1145/2950067.2950104
M3 - 会议稿件
AN - SCOPUS:84992062682
T3 - Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
SP - 143
EP - 144
BT - Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
PB - Presses Polytechniques Et Universitaires Romandes
T2 - 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
Y2 - 18 July 2016 through 20 July 2016
ER -