TY - GEN
T1 - A Resource-Adaptive, highly Parallel Hardware Accelerator for CNNs on ZYNQ-7000 SoC
AU - Li, Ying
AU - Xu, Kai
AU - Liu, Yangdong
AU - Liang, Jingzhuo
AU - Yan, Yue
AU - You, Hao
N1 - Publisher Copyright:
© 2024 Copyright held by the owner/author(s).
PY - 2024/10/28
Y1 - 2024/10/28
N2 - With the advancement of artificial intelligence and the Internet of Things, the demand for deploying neural networks on embedded devices is steadily increasing. Field Programmable Gate Arrays (FPGAs) are an optimal solution for this challenge due to their low power consumption, low latency, and programmability, which has garnered significant attention in the industry. This paper proposes a hardware accelerator architecture that leverages both the Processing System (PS) and Programmable Logic (PL) sides in parallel, based on the ZYNQ-7000 series System on Chip (SoC), and demonstrates its superior performance through the deployment of multiple convolutional models.
AB - With the advancement of artificial intelligence and the Internet of Things, the demand for deploying neural networks on embedded devices is steadily increasing. Field Programmable Gate Arrays (FPGAs) are an optimal solution for this challenge due to their low power consumption, low latency, and programmability, which has garnered significant attention in the industry. This paper proposes a hardware accelerator architecture that leverages both the Processing System (PS) and Programmable Logic (PL) sides in parallel, based on the ZYNQ-7000 series System on Chip (SoC), and demonstrates its superior performance through the deployment of multiple convolutional models.
KW - FPGA
KW - Hardware Accelerator
KW - Imgae Porcessing
UR - https://www.scopus.com/pages/publications/85210842477
U2 - 10.1145/3688863.3689574
DO - 10.1145/3688863.3689574
M3 - 会议稿件
AN - SCOPUS:85210842477
T3 - EMCLR 2024 - Proceedings of the 1st International Workshop on Efficient Multimedia Computing under Limited Resources, Co-Located with: MM 2024
SP - 8
EP - 12
BT - EMCLR 2024 - Proceedings of the 1st International Workshop on Efficient Multimedia Computing under Limited Resources, Co-Located with
PB - Association for Computing Machinery, Inc
T2 - 1st International Workshop on Efficient Multimedia Computing under Limited Resources, EMCLR 2024
Y2 - 28 October 2024 through 1 November 2024
ER -