A Generalized Center-Aligned High-Resolution Pulse Width Modulator Implementation Using an Output Serializer in Field Programmable Gate Arrays

A digital pulse width modulator (DPWM) is a key component in digital power electronics. Techniques like space vector modulation, along with rising switching frequencies from wide-bandgap power transistors, create a need for a center-aligned high-resolution PWM (CA-HRPWM). However, existing FPGA-based HRPWM designs primarily focus on achieving fine timing resolution and are not fully optimized for multichannel CA-HRPWM implementations. This paper presents a generalized CA-HRPWM design based on the output serializer (OSERDES) module. The design includes comparison values and dead time calculation, a time base and triangular carrier generation, unary code encoding, and an OSERDES-based data-to-time converter (DTC). The hardware implementation results demonstrate that the design has a minimal overhead compared with a conventional PWM generator. The proposed design achieved an 800 ps resolution for both pulse width and dead time generation with excellent linearity. Additionally, the effectiveness of the design was shown in a PMSM current controller, where it reduced the current ripple by up to 64% compared with a conventional PWM generator.