A Fully-Parallel Digital MRAM Computing-in-Memory Macro Featuring a High-Efficient Dynamic Adder Tree and Bit-Splitting MAC

Digital computing in-memory (DCIM) macros, known for their high robustness, have recently attracted growing attention. However, they still face challenges of large logic overhead and low efficiency sign-bit processing in fully-parallel CIM. In this work, we propose a fully-parallel digital MRAM-CIM architecture featuring a dynamic adder tree and a bit-splitting multiply-and-accumulate (MAC) scheme. Based on a 28 nm CMOS process and voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) devices, a 128-kb MRAM-CIM macro was simulated to validate the proposed design. The dynamic full-adder and 15-to-4 full-precision compression-based adder tree achieves 48.7% lower energy for MAC operations, while the bit-splitting approach eliminates sign-extension operations, improving computing efficiency. Furthermore, the shared voltage-divider reference cell enables compact 2T1M storage, achieving 73.96% and 64% area reduction compared with complementary cell designs. The proposed MRAM-CIM achieves energy efficiency of 96.9 TOPS/W and throughput of 2.8 TOPS at IN-8b/W-8b/OUT-22b with 0.9 V VDD. Its figure-of-merit is 3.03-5.27× higher than existing CIM macros.