A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation

Kaili Zhang; Zhongzhen Tong; Xinxin Liang; Chengzhi Wang; You Wang; Yue Zhang; Weisheng Zhao; Lang Zeng; Deming Zhang

doi:10.1109/TCSII.2023.3322556

A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation

Kaili Zhang
, Zhongzhen Tong
, Xinxin Liang
, Chengzhi Wang
, You Wang
, Yue Zhang
, Weisheng Zhao
, Lang Zeng^*
, Deming Zhang^*

^*此作品的通讯作者

集成电路科学与工程学院

Beihang University
Academy of Military Medical Science China
Nanjing University of Aeronautics and Astronautics

科研成果: 期刊稿件 › 文章 › 同行评审

10 引用（Scopus）

摘要

A charge-domain compute-in-memory (CIM) macro is proposed to implement bit-scalable multiply-and-accumulate (MAC) operation with the cell-embedded digital-to-analog (DA) conversion and two-stage analog-to-digital (AD) conversion. The cell-embedded DA conversion is achieved among the capacitances inside the proposed 12T2C SRAM CIM cell, enabling 1-4 bit input. Then, multiple columns of CIM macro are merged to form 1/2/4 bit weight by controlling the switches in the multi-bit weight switch array. The proposed two-stage AD conversion circuit for 4-b output can reduce the output cycles with high energy efficiency. By using the CMOS 55nm design kit, the simulation results show that a 4kb CIM macro can achieve a throughput of 151.70-1260.31 GOPS and energy efficiency of 97.99-419.55 TOPS/W.

源语言	英语
页（从-至）	1077-1081
页数	5
期刊	IEEE Transactions on Circuits and Systems II: Express Briefs
卷	71
期	3
DOI	https://doi.org/10.1109/TCSII.2023.3322556
出版状态	已出版 - 1 3月 2024

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title = "A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation",

abstract = "A charge-domain compute-in-memory (CIM) macro is proposed to implement bit-scalable multiply-and-accumulate (MAC) operation with the cell-embedded digital-to-analog (DA) conversion and two-stage analog-to-digital (AD) conversion. The cell-embedded DA conversion is achieved among the capacitances inside the proposed 12T2C SRAM CIM cell, enabling 1-4 bit input. Then, multiple columns of CIM macro are merged to form 1/2/4 bit weight by controlling the switches in the multi-bit weight switch array. The proposed two-stage AD conversion circuit for 4-b output can reduce the output cycles with high energy efficiency. By using the CMOS 55nm design kit, the simulation results show that a 4kb CIM macro can achieve a throughput of 151.70-1260.31 GOPS and energy efficiency of 97.99-419.55 TOPS/W.",

keywords = "Charge-domain, cell-embedded DA conversion, compute-in-memory (CIM), two-stage AD conversion",

author = "Kaili Zhang and Zhongzhen Tong and Xinxin Liang and Chengzhi Wang and You Wang and Yue Zhang and Weisheng Zhao and Lang Zeng and Deming Zhang",

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doi = "10.1109/TCSII.2023.3322556",

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T1 - A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation

AU - Zhang, Kaili

AU - Tong, Zhongzhen

AU - Liang, Xinxin

AU - Wang, Chengzhi

AU - Wang, You

AU - Zhang, Yue

AU - Zhao, Weisheng

AU - Zeng, Lang

AU - Zhang, Deming

PY - 2024/3/1

Y1 - 2024/3/1

N2 - A charge-domain compute-in-memory (CIM) macro is proposed to implement bit-scalable multiply-and-accumulate (MAC) operation with the cell-embedded digital-to-analog (DA) conversion and two-stage analog-to-digital (AD) conversion. The cell-embedded DA conversion is achieved among the capacitances inside the proposed 12T2C SRAM CIM cell, enabling 1-4 bit input. Then, multiple columns of CIM macro are merged to form 1/2/4 bit weight by controlling the switches in the multi-bit weight switch array. The proposed two-stage AD conversion circuit for 4-b output can reduce the output cycles with high energy efficiency. By using the CMOS 55nm design kit, the simulation results show that a 4kb CIM macro can achieve a throughput of 151.70-1260.31 GOPS and energy efficiency of 97.99-419.55 TOPS/W.

AB - A charge-domain compute-in-memory (CIM) macro is proposed to implement bit-scalable multiply-and-accumulate (MAC) operation with the cell-embedded digital-to-analog (DA) conversion and two-stage analog-to-digital (AD) conversion. The cell-embedded DA conversion is achieved among the capacitances inside the proposed 12T2C SRAM CIM cell, enabling 1-4 bit input. Then, multiple columns of CIM macro are merged to form 1/2/4 bit weight by controlling the switches in the multi-bit weight switch array. The proposed two-stage AD conversion circuit for 4-b output can reduce the output cycles with high energy efficiency. By using the CMOS 55nm design kit, the simulation results show that a 4kb CIM macro can achieve a throughput of 151.70-1260.31 GOPS and energy efficiency of 97.99-419.55 TOPS/W.

KW - Charge-domain

KW - cell-embedded DA conversion

KW - compute-in-memory (CIM)

KW - two-stage AD conversion

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DO - 10.1109/TCSII.2023.3322556

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JO - IEEE Transactions on Circuits and Systems II: Express Briefs

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A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation

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