A 74.5-dB DR 1.25-MHz BW Continuous-Time Delta-Sigma ADC Using Low-Noise Feedback DAC with Optimized Barrel Shifter

This paper presents a 4-bit, 3rd-order continuous -time (CT) delta-sigma modulator (DSM) for through-wall radar (TWR) applications, achieving a 1.25-MHz bandwidth. A low-noise, current-steering digital-to-analog converter (DAC) is proposed, which employs source degeneration and noise filtering to reduce its output current noise power by 2.6 dB. To further enhance linearity, an optimized barrel shifter is implemented to perform a data-weighted averaging (DWA) algorithm based on a modulo-15 element rotation scheme. Additionally, power-efficient operational amplifiers (OPAs) utilizing a hybrid Miller and feedforward compensation scheme are employed in the second and third integrators. Fabricated in 40-nm CMOS process, the proposed Analog-to-Digital Converter (ADC) achieves a measured dynamic range (DR) of 74.5 dB and a spurious-free dynamic range (SFDR) of 80.1 dB. It consumes 6.5mW from a 1.2-V supply and occupies a core active area of 0.1 mm².