A 73-dB-SNDR 2nd-Order Noise-Shaping SAR With a Low-Noise Time-Domain Comparator

This brief presents a 73-dB-SNDR 2 nd -order noise-shaping successive approximation-register (NS-SAR) analog-to-digital converter (ADC) with a low-noise time-domain comparator. In contrast to most prior works, in which a multi-input voltage-domain comparator was adopted as a signal summation circuit, the proposed NS-SAR employs a time-domain comparator to sum signals, which reduces input-referred noise by increasing the number of voltage-controlled delay stages, exhibiting high noise efficiency. Fabricated in a 65-nm CMOS process, the prototype 6-bit NS-SAR ADC achieves a peak signal-to-noise and distortion ratio (SNDR) of 73 dB over a bandwidth of 250kHz with an oversampling ratio (OSR) of 20, while consuming only 93.85μ W from a 1 V supply, leading to an SNDR-based Schreier figure of merit (FoM) of 167.3 dB.