A 16-Bit 2 MS/s Cyclic-pipelined ADC with Calibration for Inter-stage Amplification

The inaccuracy of residue amplification has become the major bottleneck when it comes to design pipelined analogue-to-digital converters (ADCs). High-gain and high-speed operational amplifiers (Op-Amps) usually consume too much power for a decent ADC. Therefore, we proposed a foreground calibration technique, which can correct amplification errors in cyclic-pipelined ADCs and consequently alleviate the DC gain requirement for internal amplifiers. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 5-bit sub-ADC four times, and each time 1-bit redundancy is exploited to suppress the errors due to sub-ADCs. Actual gain of each amplification can be feasibly calculated by the Fix-Point Iteration algorithm. Simulation results show the signal-to-noise-and-distortion-ratio (SINAD) to be 100.6 dB even with a 57dB-DC-Gain amplifier. The total power consumption of ADC is 30.43 mW and it occupies an active area of 1.8 mm square.