摘要
Among various cryptographic algorithms, the SM4 block cipher stands out for its simplicity and efficiency, particularly when implemented on hardware. Consequently, it has found widespread applications in encrypted transmission, encrypted storage, and beyond. As the utilization of the SM4 algorithm continues to grow, the necessity for superior hardware encryption capabilities is also increased. Recently, the implementation of the SM4 algorithm on ASIC has demonstrated high throughput in electronic code book (ECB) mode, thanks to the utilization of pipelining technology. However, in cipher block chaining (CBC) mode, achieving similar throughput improvements through pipelining is challenging due to the dependency among adjacent data blocks. To tackle this issue, we introduce two innovative simplification techniques, applied to the round function iteration process and S-box substitution process respectively. ASIC synthesis results using TSMC 40 nm technology confirm that our design achieves a throughput rate of 4.2 Gb/s in CBC mode, with a remarkable throughput of 129.4 Gb·s−1·mm−2, outperforming previously published designs in this domain.
| 投稿的翻译标题 | Efficient Design and Implementation of SM4 Algorithm with CBC Mode |
|---|---|
| 源语言 | 繁体中文 |
| 页(从-至) | 1450-1457 |
| 页数 | 8 |
| 期刊 | Jisuanji Yanjiu yu Fazhan/Computer Research and Development |
| 卷 | 61 |
| 期 | 6 |
| DOI | |
| 出版状态 | 已出版 - 2024 |
关键词
- ASIC
- CBC mode
- SM4 algorithm
- hardware acceleration
- high-efficiency design
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