Zero-skew clock network synthesis for monolithic 3D ICs with minimum wirelength

Clock network synthesis has traditionally been an important step of the physical design process, greatly affecting the performance of ICs. In this paper, we focus on the clock network design process for monolithic 3D (M3D) ICs. Firstly, we investigate the difference between Monolithic Inter-tier Via (MIV) and Through-Silicon Via (TSV) due to the different fabrication process and explore the ramifications of clock network design for monolithic 3D systems. Secondly, we develop a two step clock network synthesis algorithm (M3D-ZST) based on clustering and the deferred-merge embedding algorithm. The proposed algorithm considers the MIV characteristics and constructs a zero-skew clock tree considering wirelength optimization. Furthermore, we apply a look-ahead approach, thereby determining the optimal locations of the merging segments and MIVs such that the wirelength is reduced further (M3D-ZSTLA). Experimental results indicate that M3D-ZST algorithm reduces the total wirelength by 9.7% - 19.7%, and reduces power by 9.4% - 18.6% compared to the 3D-MMM algorithm over IBM benchmarks. The M3D-ZSTLA algorithm further decreases the total wirelength by about 3%, and reduces the power by about 2%.