U-Net Hardware Acceleration Design Based on FPGA

U-Net networks are a new type derived from fully convolutional networks (FCNs), which perform excellently in image segmentation, noise suppression, and other aspects. However, due to their deep network structure, there is a great demand for data calculation, storage, and for their performance. Therefore, hardware accelerators are increasingly needed to support this type of network to reduce inference delay and improve energy efficiency, enabling it to be deployed in real-time applications. Field-programmable gate arrays (FPGAs) can support high reconfigurability and provide superior energy efficiency and low latency processing. Therefore, FPGAs have been widely used for convolutional neural networks (CNNs) acceleration and are even more conducive to the inference calculation of U-Net. This paper researches U-Net networks, introduces hardware optimization methods, designs specific hardware architecture, conducts comprehensive design simulation, and analyses simulation results.