TY - GEN
T1 - Towards in-network acceleration of erasure coding
AU - Qiao, Yi
AU - Kong, Xiao
AU - Zhang, Menghao
AU - Zhou, Yu
AU - Xu, Mingwei
AU - Bi, Jun
N1 - Publisher Copyright:
© 2020 Association for Computing Machinery.
PY - 2020/3/3
Y1 - 2020/3/3
N2 - In distributed storage systems, erasure coding (EC) is a crucial technology to enable high fault tolerance with lower storage overheads than data replication. EC can reconstruct missing data by downloading parity data from survived machines. However, downloading streams of EC multiplex the available network I/O on the receiving end, leading to a substantially low data reconstruction speed. In this paper, we present NetEC, a novel in-network accelerating system that fully offloads EC to programmable switching ASICs. NetEC prevents multiplexing network I/O through on-switch downloading stream aggregation, thus significantly improving reconstruction speed. NetEC addresses three key challenges: computation offloading of complex EC operations, rate synchronization of multiple downloading streams, and deep payload inspection/assembly. We implement NetEC on hardware programmable switches. Evaluation shows that compared to HDFS-EC, NetEC significantly improves reconstruction rate by 2.7x-9.0x and eliminates CPU overheads, with low switch memory usage.
AB - In distributed storage systems, erasure coding (EC) is a crucial technology to enable high fault tolerance with lower storage overheads than data replication. EC can reconstruct missing data by downloading parity data from survived machines. However, downloading streams of EC multiplex the available network I/O on the receiving end, leading to a substantially low data reconstruction speed. In this paper, we present NetEC, a novel in-network accelerating system that fully offloads EC to programmable switching ASICs. NetEC prevents multiplexing network I/O through on-switch downloading stream aggregation, thus significantly improving reconstruction speed. NetEC addresses three key challenges: computation offloading of complex EC operations, rate synchronization of multiple downloading streams, and deep payload inspection/assembly. We implement NetEC on hardware programmable switches. Evaluation shows that compared to HDFS-EC, NetEC significantly improves reconstruction rate by 2.7x-9.0x and eliminates CPU overheads, with low switch memory usage.
KW - Erasure coding
KW - Programmable switches
UR - https://www.scopus.com/pages/publications/85082168454
U2 - 10.1145/3373360.3380833
DO - 10.1145/3373360.3380833
M3 - 会议稿件
AN - SCOPUS:85082168454
T3 - SOSR 2020 - Proceedings of the 2020 Symposium on SDN Research
SP - 41
EP - 47
BT - SOSR 2020 - Proceedings of the 2020 Symposium on SDN Research
PB - Association for Computing Machinery, Inc
T2 - 2020 Symposium on SDN Research, SOSR 2020
Y2 - 3 March 2020
ER -