Towards in-network acceleration of erasure coding

  • Yi Qiao
  • , Xiao Kong
  • , Menghao Zhang
  • , Yu Zhou
  • , Mingwei Xu*
  • , Jun Bi
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In distributed storage systems, erasure coding (EC) is a crucial technology to enable high fault tolerance with lower storage overheads than data replication. EC can reconstruct missing data by downloading parity data from survived machines. However, downloading streams of EC multiplex the available network I/O on the receiving end, leading to a substantially low data reconstruction speed. In this paper, we present NetEC, a novel in-network accelerating system that fully offloads EC to programmable switching ASICs. NetEC prevents multiplexing network I/O through on-switch downloading stream aggregation, thus significantly improving reconstruction speed. NetEC addresses three key challenges: computation offloading of complex EC operations, rate synchronization of multiple downloading streams, and deep payload inspection/assembly. We implement NetEC on hardware programmable switches. Evaluation shows that compared to HDFS-EC, NetEC significantly improves reconstruction rate by 2.7x-9.0x and eliminates CPU overheads, with low switch memory usage.

Original languageEnglish
Title of host publicationSOSR 2020 - Proceedings of the 2020 Symposium on SDN Research
PublisherAssociation for Computing Machinery, Inc
Pages41-47
Number of pages7
ISBN (Electronic)9781450371018
DOIs
StatePublished - 3 Mar 2020
Externally publishedYes
Event2020 Symposium on SDN Research, SOSR 2020 - San Jose, United States
Duration: 3 Mar 2020 → …

Publication series

NameSOSR 2020 - Proceedings of the 2020 Symposium on SDN Research

Conference

Conference2020 Symposium on SDN Research, SOSR 2020
Country/TerritoryUnited States
CitySan Jose
Period3/03/20 → …

Keywords

  • Erasure coding
  • Programmable switches

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