TY - GEN
T1 - Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture
AU - Li, Yueting
AU - Zhang, He
AU - Wang, Xueyan
AU - Cai, Hao
AU - Zhang, Yundong
AU - Lv, Shuqin
AU - Liu, Renguang
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2023 Copyright held by the owner/author(s).
PY - 2023/1/16
Y1 - 2023/1/16
N2 - Sparse Matrix-Vector Multiplication (SpMV) is one of the vital computational primitives used in modern workloads. SpMV performs memory access, leading to unnecessary data transmission, massive data access, and redundant multiplicative accumulators. Therefore, we propose the near spin-transfer torque magnetic random access memory (STT-MRAM) processing architecture from three optimization perspectives. These optimizations include (1) the NMP controller receives the instruction through the AXI4 bus to implement the SpMV operation in the following steps, identifies valid data, and encodes the index depending on the kernel size, (2) the NMP controller uses high-level synthesis dataflow in the shared buffer for achieving better performance throughput while do not consume bus bandwidth, and (3) the configurable MACs are implemented in the NMP core without matching step entirely during the multiplication. Using these optimizations, the NMP architecture can access the pipelined STT-MRAM (read bandwidth is 26.7GB/s). The experimental simulation results show that this design achieves up to 66x and 28x speedup compared with state-of-the-art ones and 69x speedup without sparse optimization.
AB - Sparse Matrix-Vector Multiplication (SpMV) is one of the vital computational primitives used in modern workloads. SpMV performs memory access, leading to unnecessary data transmission, massive data access, and redundant multiplicative accumulators. Therefore, we propose the near spin-transfer torque magnetic random access memory (STT-MRAM) processing architecture from three optimization perspectives. These optimizations include (1) the NMP controller receives the instruction through the AXI4 bus to implement the SpMV operation in the following steps, identifies valid data, and encodes the index depending on the kernel size, (2) the NMP controller uses high-level synthesis dataflow in the shared buffer for achieving better performance throughput while do not consume bus bandwidth, and (3) the configurable MACs are implemented in the NMP core without matching step entirely during the multiplication. Using these optimizations, the NMP architecture can access the pipelined STT-MRAM (read bandwidth is 26.7GB/s). The experimental simulation results show that this design achieves up to 66x and 28x speedup compared with state-of-the-art ones and 69x speedup without sparse optimization.
KW - Energy Efficient
KW - Near Memory Processing
KW - STT-MRAM
KW - SpMV
UR - https://www.scopus.com/pages/publications/85148487600
U2 - 10.1145/3566097.3567859
DO - 10.1145/3566097.3567859
M3 - 会议稿件
AN - SCOPUS:85148487600
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 222
EP - 227
BT - ASP-DAC 2023 - 28th Asia and South Pacific Design Automation Conference, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 28th Asia and South Pacific Design Automation Conference, ASP-DAC 2023
Y2 - 16 January 2023 through 19 January 2023
ER -