Supporting transaction nesting in hardware transactional memory

Transactional memory is an attractive technology to improve programmability of multi-core processors. However, there still exist challenges for hardware transactional memory including efficient transaction nesting. To support closed nesting efficiently without increasing hardware complexities significantly, this paper proposes a CPR scheme which supports conditional partial rollback on conflict. In stead of rolling back to the outermost transaction as in commonly-used flattening model, the CPR scheme just rolls back to the conflicted transaction itself or one of its outer-level transactions if given condition is satisfied. By adding a series of hardware bits in transactional buffer to record read/write status of each nested transaction, the CPR scheme only maintains a global data set for all of the nested transactions rather than independent data set for each nested transaction as in nested LogTM. Evaluation results show that the CPR scheme achieves similar performance with the nested LogTM, and is better than the flattening model.