Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology

Xi Tian; Xuelian Zhang; Yuping Wu; Zhiqiang Li; Hongge Li; Shushan Qian

doi:10.1145/3776942.3776977

Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology

Xi Tian
, Xuelian Zhang
, Yuping Wu^*
, Zhiqiang Li
, Hongge Li
, Shushan Qian

^*Corresponding author for this work

School of Electronic and Information Engineering

University of Chinese Academy of Sciences
CAS - Institute of Microelectronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents an ultra-low-power subthreshold logic synthesis with bootstrapped sensitive amplifier-Pass transistor logic (B-SAPTL) topology. The design synergizes subthreshold operation's energy efficiency with bootstrapping-enhanced performance and sensitive amplifier-based noise resilience. Our approach overcomes conventional limitations of speed degradation and poor noise margins in subthreshold logic. The proposed synthesis methodology optimizes energy-delay tradeoffs while maintaining variation tolerance. By using B- SAPTL subthreshold logic synthesis, the designed B- SAPTL 16bit adder in 130nm technology achieved 3.59X faster and 66.5% lower energy-delay product than subthreshold standard cell based CLA adder, enabling reliable operation down to 0.2V. These advances make the technique particularly suitable for biomedical implants and IoT edge devices requiring minimum-energy computation. The work provides a systematic framework for synthesizing robust and high-performance subthreshold circuits.

Original language	English
Title of host publication	ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers
Editors	MA. Jabbar, Anand Nayyar, Atanaska Bosakova-Ardenska, Cheng Hu
Publisher	Association for Computing Machinery, Inc
Pages	41-45
Number of pages	5
ISBN (Electronic)	9798400715839
DOIs	https://doi.org/10.1145/3776942.3776977
State	Published - 22 Dec 2025
Event	11th Annual International Conference on Network and Information Systems for Computers, ICNISC 2025 - Wuhan, China Duration: 22 Aug 2025 → 24 Aug 2025

Publication series

Name	ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers

Conference

Conference	11th Annual International Conference on Network and Information Systems for Computers, ICNISC 2025
Country/Territory	China
City	Wuhan
Period	22/08/25 → 24/08/25

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Bootstrapped sensitive amplifier-pass transistor logic (B-SAPTL)
Logic synthesis
Subthreshold circuits

Access to Document

10.1145/3776942.3776977

Cite this

Tian, X., Zhang, X., Wu, Y., Li, Z., Li, H., & Qian, S. (2025). Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology. In MA. Jabbar, A. Nayyar, A. Bosakova-Ardenska, & C. Hu (Eds.), ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers (pp. 41-45). (ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers). Association for Computing Machinery, Inc. https://doi.org/10.1145/3776942.3776977

Tian, Xi ; Zhang, Xuelian ; Wu, Yuping et al. / Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology. ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers. editor / MA. Jabbar ; Anand Nayyar ; Atanaska Bosakova-Ardenska ; Cheng Hu. Association for Computing Machinery, Inc, 2025. pp. 41-45 (ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers).

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title = "Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology",

abstract = "This paper presents an ultra-low-power subthreshold logic synthesis with bootstrapped sensitive amplifier-Pass transistor logic (B-SAPTL) topology. The design synergizes subthreshold operation's energy efficiency with bootstrapping-enhanced performance and sensitive amplifier-based noise resilience. Our approach overcomes conventional limitations of speed degradation and poor noise margins in subthreshold logic. The proposed synthesis methodology optimizes energy-delay tradeoffs while maintaining variation tolerance. By using B- SAPTL subthreshold logic synthesis, the designed B- SAPTL 16bit adder in 130nm technology achieved 3.59X faster and 66.5\% lower energy-delay product than subthreshold standard cell based CLA adder, enabling reliable operation down to 0.2V. These advances make the technique particularly suitable for biomedical implants and IoT edge devices requiring minimum-energy computation. The work provides a systematic framework for synthesizing robust and high-performance subthreshold circuits.",

keywords = "Bootstrapped sensitive amplifier-pass transistor logic (B-SAPTL), Logic synthesis, Subthreshold circuits",

author = "Xi Tian and Xuelian Zhang and Yuping Wu and Zhiqiang Li and Hongge Li and Shushan Qian",

note = "Publisher Copyright: {\textcopyright} 2025 Copyright held by the owner/author(s).; 11th Annual International Conference on Network and Information Systems for Computers, ICNISC 2025 ; Conference date: 22-08-2025 Through 24-08-2025",

year = "2025",

month = dec,

day = "22",

doi = "10.1145/3776942.3776977",

language = "英语",

series = "ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers",

publisher = "Association for Computing Machinery, Inc",

pages = "41--45",

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Tian, X, Zhang, X, Wu, Y, Li, Z, Li, H & Qian, S 2025, Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology. in MA Jabbar, A Nayyar, A Bosakova-Ardenska & C Hu (eds), ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers. ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers, Association for Computing Machinery, Inc, pp. 41-45, 11th Annual International Conference on Network and Information Systems for Computers, ICNISC 2025, Wuhan, China, 22/08/25. https://doi.org/10.1145/3776942.3776977

Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology. / Tian, Xi; Zhang, Xuelian; Wu, Yuping et al.
ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers. ed. / MA. Jabbar; Anand Nayyar; Atanaska Bosakova-Ardenska; Cheng Hu. Association for Computing Machinery, Inc, 2025. p. 41-45 (ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology

AU - Tian, Xi

AU - Zhang, Xuelian

AU - Wu, Yuping

AU - Li, Zhiqiang

AU - Li, Hongge

AU - Qian, Shushan

PY - 2025/12/22

Y1 - 2025/12/22

N2 - This paper presents an ultra-low-power subthreshold logic synthesis with bootstrapped sensitive amplifier-Pass transistor logic (B-SAPTL) topology. The design synergizes subthreshold operation's energy efficiency with bootstrapping-enhanced performance and sensitive amplifier-based noise resilience. Our approach overcomes conventional limitations of speed degradation and poor noise margins in subthreshold logic. The proposed synthesis methodology optimizes energy-delay tradeoffs while maintaining variation tolerance. By using B- SAPTL subthreshold logic synthesis, the designed B- SAPTL 16bit adder in 130nm technology achieved 3.59X faster and 66.5% lower energy-delay product than subthreshold standard cell based CLA adder, enabling reliable operation down to 0.2V. These advances make the technique particularly suitable for biomedical implants and IoT edge devices requiring minimum-energy computation. The work provides a systematic framework for synthesizing robust and high-performance subthreshold circuits.

AB - This paper presents an ultra-low-power subthreshold logic synthesis with bootstrapped sensitive amplifier-Pass transistor logic (B-SAPTL) topology. The design synergizes subthreshold operation's energy efficiency with bootstrapping-enhanced performance and sensitive amplifier-based noise resilience. Our approach overcomes conventional limitations of speed degradation and poor noise margins in subthreshold logic. The proposed synthesis methodology optimizes energy-delay tradeoffs while maintaining variation tolerance. By using B- SAPTL subthreshold logic synthesis, the designed B- SAPTL 16bit adder in 130nm technology achieved 3.59X faster and 66.5% lower energy-delay product than subthreshold standard cell based CLA adder, enabling reliable operation down to 0.2V. These advances make the technique particularly suitable for biomedical implants and IoT edge devices requiring minimum-energy computation. The work provides a systematic framework for synthesizing robust and high-performance subthreshold circuits.

KW - Bootstrapped sensitive amplifier-pass transistor logic (B-SAPTL)

KW - Logic synthesis

KW - Subthreshold circuits

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DO - 10.1145/3776942.3776977

M3 - 会议稿件

AN - SCOPUS:105026665176

T3 - ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers

SP - 41

EP - 45

BT - ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers

A2 - Jabbar, MA.

A2 - Nayyar, Anand

A2 - Bosakova-Ardenska, Atanaska

A2 - Hu, Cheng

PB - Association for Computing Machinery, Inc

T2 - 11th Annual International Conference on Network and Information Systems for Computers, ICNISC 2025

Y2 - 22 August 2025 through 24 August 2025

ER -

Tian X, Zhang X, Wu Y, Li Z, Li H, Qian S. Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology. In Jabbar MA, Nayyar A, Bosakova-Ardenska A, Hu C, editors, ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers. Association for Computing Machinery, Inc. 2025. p. 41-45. (ICNISC 2025 - 11th Annual International Conference on Network and Information Systems for Computers). doi: 10.1145/3776942.3776977

Subthreshold Logic Synthesis with Bootstrapped SAPTL-based Circuit Topology

Abstract

Publication series

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UN SDGs

Keywords

Access to Document

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