Study on the decoder for reed-solomon (255, 239) code

Yue Tao Ge; Xiao Ming Liu; Xiao Tong Yin

doi:10.4028/www.scientific.net/AMM.482.390

Study on the decoder for reed-solomon (255, 239) code

Yue Tao Ge
, Xiao Ming Liu
, Xiao Tong Yin

Beijing HIWING Scientific and Technological Information Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Reed Solomon code is described as a theoretical decoder that corrected errors by finding the most popular message polynomial. The Verilog language is applied to descript decoding algorithm. Cyclone series FPGA EP1C6Q240C8 is adopted as a core of hardware platform and a serial port communication part is used to receive input error correction data. The results show that it can successfully correct eight errors, which is the limitation of error correction. With the RS decoder, it can ensure that the strong error correction capability and fast speed.

Original language	English
Title of host publication	Structural Engineering, Vibration and Aerospace Engineering
Pages	390-393
Number of pages	4
DOIs	https://doi.org/10.4028/www.scientific.net/AMM.482.390
State	Published - 2014
Externally published	Yes
Event	2013 International Conference on Structural Engineering, Vibration and Aerospace Engineering, SEVAE 2013 - Zhuhai, China Duration: 23 Nov 2013 → 24 Nov 2013

Publication series

Name	Applied Mechanics and Materials
Volume	482
ISSN (Print)	1660-9336
ISSN (Electronic)	1662-7482

Conference

Conference	2013 International Conference on Structural Engineering, Vibration and Aerospace Engineering, SEVAE 2013
Country/Territory	China
City	Zhuhai
Period	23/11/13 → 24/11/13

Keywords

Decoder
FPGA
Reed-solomon (255, 239)
Verilog

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10.4028/www.scientific.net/AMM.482.390

Cite this

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title = "Study on the decoder for reed-solomon (255, 239) code",

abstract = "Reed Solomon code is described as a theoretical decoder that corrected errors by finding the most popular message polynomial. The Verilog language is applied to descript decoding algorithm. Cyclone series FPGA EP1C6Q240C8 is adopted as a core of hardware platform and a serial port communication part is used to receive input error correction data. The results show that it can successfully correct eight errors, which is the limitation of error correction. With the RS decoder, it can ensure that the strong error correction capability and fast speed.",

keywords = "Decoder, FPGA, Reed-solomon (255, 239), Verilog",

author = "Ge, \{Yue Tao\} and Liu, \{Xiao Ming\} and Yin, \{Xiao Tong\}",

year = "2014",

doi = "10.4028/www.scientific.net/AMM.482.390",

language = "英语",

isbn = "9783037859858",

series = "Applied Mechanics and Materials",

pages = "390--393",

booktitle = "Structural Engineering, Vibration and Aerospace Engineering",

note = "2013 International Conference on Structural Engineering, Vibration and Aerospace Engineering, SEVAE 2013 ; Conference date: 23-11-2013 Through 24-11-2013",

}

Ge, YT, Liu, XM & Yin, XT 2014, Study on the decoder for reed-solomon (255, 239) code. in Structural Engineering, Vibration and Aerospace Engineering. Applied Mechanics and Materials, vol. 482, pp. 390-393, 2013 International Conference on Structural Engineering, Vibration and Aerospace Engineering, SEVAE 2013, Zhuhai, China, 23/11/13. https://doi.org/10.4028/www.scientific.net/AMM.482.390

TY - GEN

T1 - Study on the decoder for reed-solomon (255, 239) code

AU - Ge, Yue Tao

AU - Liu, Xiao Ming

AU - Yin, Xiao Tong

PY - 2014

Y1 - 2014

N2 - Reed Solomon code is described as a theoretical decoder that corrected errors by finding the most popular message polynomial. The Verilog language is applied to descript decoding algorithm. Cyclone series FPGA EP1C6Q240C8 is adopted as a core of hardware platform and a serial port communication part is used to receive input error correction data. The results show that it can successfully correct eight errors, which is the limitation of error correction. With the RS decoder, it can ensure that the strong error correction capability and fast speed.

AB - Reed Solomon code is described as a theoretical decoder that corrected errors by finding the most popular message polynomial. The Verilog language is applied to descript decoding algorithm. Cyclone series FPGA EP1C6Q240C8 is adopted as a core of hardware platform and a serial port communication part is used to receive input error correction data. The results show that it can successfully correct eight errors, which is the limitation of error correction. With the RS decoder, it can ensure that the strong error correction capability and fast speed.

KW - Decoder

KW - FPGA

KW - Reed-solomon (255, 239)

KW - Verilog

UR - https://www.scopus.com/pages/publications/84892149433

U2 - 10.4028/www.scientific.net/AMM.482.390

DO - 10.4028/www.scientific.net/AMM.482.390

M3 - 会议稿件

AN - SCOPUS:84892149433

SN - 9783037859858

T3 - Applied Mechanics and Materials

SP - 390

EP - 393

BT - Structural Engineering, Vibration and Aerospace Engineering

T2 - 2013 International Conference on Structural Engineering, Vibration and Aerospace Engineering, SEVAE 2013

Y2 - 23 November 2013 through 24 November 2013

ER -

Study on the decoder for reed-solomon (255, 239) code

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Keywords

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