TY - GEN
T1 - Static Timing Analysis Acceleration to Attack Process Corner Explosion by Matrix Filling Prediction
AU - Wang, Longze
AU - Wang, Zhelong
AU - Xing, Wei X.
AU - Xu, Ning
AU - Cheng, Yuanqing
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Static timing analysis (STA) is a highly effective procedure required for modern advanced nanoscale integrated circuit design. However, the increasing number of process corners has made performing STA analysis at each physical design stage time-consuming. To enhance efficiency, we propose MCSTA, a point-wise imputation method, to predict timing path delay under different process corners. We formulate it as a partial matrix completion problem and solve it using a neural network-based timing prediction algorithm. Unlike previous methods that rely on full-timing simulations under the specific process corner, our algorithm captures timing information from only a few timing paths, significantly reducing run time overhead. We further optimize timing prediction accuracy using autoencoders to capture relationships between timing paths and process corners. Additionally, we introduce an active learning algorithm adapted for point-wise imputation to utilize timing information from previous design stages, minimizing the required number of timing simulations and improving prediction performance. Experimental results show that our method achieves nearly 100 % accuracy with a limited number of path timings while reducing run time overhead by orders of magnitude compared to conventional STA analysis.
AB - Static timing analysis (STA) is a highly effective procedure required for modern advanced nanoscale integrated circuit design. However, the increasing number of process corners has made performing STA analysis at each physical design stage time-consuming. To enhance efficiency, we propose MCSTA, a point-wise imputation method, to predict timing path delay under different process corners. We formulate it as a partial matrix completion problem and solve it using a neural network-based timing prediction algorithm. Unlike previous methods that rely on full-timing simulations under the specific process corner, our algorithm captures timing information from only a few timing paths, significantly reducing run time overhead. We further optimize timing prediction accuracy using autoencoders to capture relationships between timing paths and process corners. Additionally, we introduce an active learning algorithm adapted for point-wise imputation to utilize timing information from previous design stages, minimizing the required number of timing simulations and improving prediction performance. Experimental results show that our method achieves nearly 100 % accuracy with a limited number of path timings while reducing run time overhead by orders of magnitude compared to conventional STA analysis.
KW - Active Learning
KW - Machine Learning
KW - Matrix Completion
KW - Point-wise Imputation
KW - Static Timing Analysis
UR - https://www.scopus.com/pages/publications/85201733901
U2 - 10.1109/ISEDA62518.2024.10617500
DO - 10.1109/ISEDA62518.2024.10617500
M3 - 会议稿件
AN - SCOPUS:85201733901
T3 - 2024 International Symposium of Electronics Design Automation, ISEDA 2024
SP - 398
EP - 403
BT - 2024 International Symposium of Electronics Design Automation, ISEDA 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 International Symposium of Electronics Design Automation, ISEDA 2024
Y2 - 10 May 2024 through 13 May 2024
ER -