Spintronic Processing Unit Within Voltage-Gated Spin Hall Effect MRAMs

Realization of the unity of processing and storage in the same chip/die has initialized a promising research direction of processing-in-memory (PIM), attempting to address the 'memory wall' challenge in typical von-Neumann computing architectures. Nevertheless, there still exist many issues, which require an efficient implementation of PIM. In this paper, we propose a novel PIM paradigm and architecture to support a spintronic processing unit (SPU), within voltage-gated spin Hall effect driven MRAMs. Different from previous studies, the data initially stored in the memory units are treated as logic input operands and the logic output results are in situ stored in the memory units themselves. More importantly, the proposed SPU works just like a typical memory, and all the logic functions are achieved through regular memory-like read/write operations. Besides, a 1-b full adder based on different array structures (including typical array and crossbar array) is implemented and the possibility of block parallel is discussed. Furthermore, we propose a novel reconfigure architecture, which efficiently translates logical tasks into concrete regular memory-like read/write operations, to support the SPU. Under the 40 nm process technology node, the proposed 1-b full adder can achieve ∼20.00 ns/b (∼8.33 ns/b) and ∼63.8 fJ/b (∼77.35 fJ/b) based on the typical array (crossbar array) structure.