Spinsim: A computer architecture-level variation aware STT-MRAM performance evaluation framework

Haoyuan Ma; You Wang; Rashid Ali; Zhengyi Hou; Deming Zhang; Erya Deng; Gefei Wang; Weisheng Zhao

doi:10.1109/ISCAS51556.2021.9401359

Spinsim: A computer architecture-level variation aware STT-MRAM performance evaluation framework

Haoyuan Ma
, You Wang^*
, Rashid Ali
, Zhengyi Hou
, Deming Zhang
, Erya Deng
, Gefei Wang
, Weisheng Zhao

^*Corresponding author for this work

School of Integrated Circuit Science and Engineering

Beihang University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

With low power consumption, fast access speed, high scalability and infinite endurance, spin-transfer torque magnetoresistive random access memory (STT-MRAM) is considered as one of the most promising alternatives to SRAM. However, The performance of STT-MRAM is significantly influenced by several reliability issues, such as process variations and stochastic switching. Most of the reliability analysis of relative circuits are performed at bit-cell and memory level, while that at computer-system level is missing. This paper proposes an efficient framework for performance evaluation of STT-MRAM on computer architecture-level implemented by GEM5+NVMain co-simulator in consideration of the reliability issues. The results show that the overall average latency and energy of STT-MRAM can be up to 5.996% and 20.65% larger than that of the nominal cases in a computer system-level memory architecture taking reliability issues into account. Because reliability issues are considered during the design phase, our framework can provide more accurate performance evaluation and contribute to a higher yield of STT-MRAM based computer systems.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728192017
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401359
State	Published - 2021
Event	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2021-May
ISSN (Print)	0271-4310

Conference

Conference	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/Territory	Korea, Republic of
City	Daegu
Period	22/05/21 → 28/05/21

Keywords

Non-volatile memory
Performance evaluation
Process variation
Reliability
Spin-transfer torque magnetic random access memory (STT-MRAM)

Access to Document

10.1109/ISCAS51556.2021.9401359

Cite this

Ma, H., Wang, Y., Ali, R., Hou, Z., Zhang, D., Deng, E., Wang, G., & Zhao, W. (2021). Spinsim: A computer architecture-level variation aware STT-MRAM performance evaluation framework. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings Article 9401359 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS51556.2021.9401359

@inproceedings{b07e1fad814a4f2394ce6fb8cd730df8,

title = "Spinsim: A computer architecture-level variation aware STT-MRAM performance evaluation framework",

abstract = "With low power consumption, fast access speed, high scalability and infinite endurance, spin-transfer torque magnetoresistive random access memory (STT-MRAM) is considered as one of the most promising alternatives to SRAM. However, The performance of STT-MRAM is significantly influenced by several reliability issues, such as process variations and stochastic switching. Most of the reliability analysis of relative circuits are performed at bit-cell and memory level, while that at computer-system level is missing. This paper proposes an efficient framework for performance evaluation of STT-MRAM on computer architecture-level implemented by GEM5+NVMain co-simulator in consideration of the reliability issues. The results show that the overall average latency and energy of STT-MRAM can be up to 5.996\% and 20.65\% larger than that of the nominal cases in a computer system-level memory architecture taking reliability issues into account. Because reliability issues are considered during the design phase, our framework can provide more accurate performance evaluation and contribute to a higher yield of STT-MRAM based computer systems.",

keywords = "Non-volatile memory, Performance evaluation, Process variation, Reliability, Spin-transfer torque magnetic random access memory (STT-MRAM)",

author = "Haoyuan Ma and You Wang and Rashid Ali and Zhengyi Hou and Deming Zhang and Erya Deng and Gefei Wang and Weisheng Zhao",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",

year = "2021",

doi = "10.1109/ISCAS51556.2021.9401359",

language = "英语",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings",

address = "美国",

}

Ma, H, Wang, Y, Ali, R, Hou, Z, Zhang, D, Deng, E, Wang, G & Zhao, W 2021, Spinsim: A computer architecture-level variation aware STT-MRAM performance evaluation framework. in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401359, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, Institute of Electrical and Electronics Engineers Inc., 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401359

Spinsim: A computer architecture-level variation aware STT-MRAM performance evaluation framework. / Ma, Haoyuan; Wang, You; Ali, Rashid et al.
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9401359 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Spinsim

T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021

AU - Ma, Haoyuan

AU - Wang, You

AU - Ali, Rashid

AU - Hou, Zhengyi

AU - Zhang, Deming

AU - Deng, Erya

AU - Wang, Gefei

AU - Zhao, Weisheng

PY - 2021

Y1 - 2021

N2 - With low power consumption, fast access speed, high scalability and infinite endurance, spin-transfer torque magnetoresistive random access memory (STT-MRAM) is considered as one of the most promising alternatives to SRAM. However, The performance of STT-MRAM is significantly influenced by several reliability issues, such as process variations and stochastic switching. Most of the reliability analysis of relative circuits are performed at bit-cell and memory level, while that at computer-system level is missing. This paper proposes an efficient framework for performance evaluation of STT-MRAM on computer architecture-level implemented by GEM5+NVMain co-simulator in consideration of the reliability issues. The results show that the overall average latency and energy of STT-MRAM can be up to 5.996% and 20.65% larger than that of the nominal cases in a computer system-level memory architecture taking reliability issues into account. Because reliability issues are considered during the design phase, our framework can provide more accurate performance evaluation and contribute to a higher yield of STT-MRAM based computer systems.

AB - With low power consumption, fast access speed, high scalability and infinite endurance, spin-transfer torque magnetoresistive random access memory (STT-MRAM) is considered as one of the most promising alternatives to SRAM. However, The performance of STT-MRAM is significantly influenced by several reliability issues, such as process variations and stochastic switching. Most of the reliability analysis of relative circuits are performed at bit-cell and memory level, while that at computer-system level is missing. This paper proposes an efficient framework for performance evaluation of STT-MRAM on computer architecture-level implemented by GEM5+NVMain co-simulator in consideration of the reliability issues. The results show that the overall average latency and energy of STT-MRAM can be up to 5.996% and 20.65% larger than that of the nominal cases in a computer system-level memory architecture taking reliability issues into account. Because reliability issues are considered during the design phase, our framework can provide more accurate performance evaluation and contribute to a higher yield of STT-MRAM based computer systems.

KW - Non-volatile memory

KW - Performance evaluation

KW - Process variation

KW - Reliability

KW - Spin-transfer torque magnetic random access memory (STT-MRAM)

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DO - 10.1109/ISCAS51556.2021.9401359

M3 - 会议稿件

AN - SCOPUS:85109015473

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 22 May 2021 through 28 May 2021

ER -

Ma H, Wang Y, Ali R, Hou Z, Zhang D, Deng E et al. Spinsim: A computer architecture-level variation aware STT-MRAM performance evaluation framework. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9401359. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS51556.2021.9401359

Spinsim: A computer architecture-level variation aware STT-MRAM performance evaluation framework

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