Abstract
This study introduces HWCIM, a SRAM-based Computing-In-Memory core, and SHWCIM, a CIM-capable Coarse-Grained Reconfigurable Architecture, to enhance re-source utilization, multi-functionality, and on-chip memory size in SRAM-based CIM designs. Evaluated using the SMIC 55nm process, HWCIM achieves 1.6x lower power, 2.8x higher energy efficiency, and up to 4.1x smaller area compared to previous CIM and CGRA works. Additionally, SHWCIM delivers an average 105.9x speedup over existing CGRAs and consumes 2-5x less energy than the Nvidia A40 GPU on realistic workloads.
| Original language | English |
|---|---|
| Title of host publication | 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9783982674100 |
| DOIs | |
| State | Published - 2025 |
| Event | 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Lyon, France Duration: 31 Mar 2025 → 2 Apr 2025 |
Publication series
| Name | Proceedings -Design, Automation and Test in Europe, DATE |
|---|---|
| ISSN (Print) | 1530-1591 |
Conference
| Conference | 2025 Design, Automation and Test in Europe Conference, DATE 2025 |
|---|---|
| Country/Territory | France |
| City | Lyon |
| Period | 31/03/25 → 2/04/25 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 7 Affordable and Clean Energy
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