SD-PUF: An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits

K. W. Xu; D. R. Zhang; Y. Q. Cheng

doi:10.1109/APCCAS51387.2021.9687714

SD-PUF: An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits

K. W. Xu
, D. R. Zhang
, Y. Q. Cheng

School of Integrated Circuit Science and Engineering

Beihang University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

As the hardware security gets more and more attentions, Physically Unclonable Function (PUF) has been proposed to provide chip authentication and Intellectual Property protection effectively. The traditional PUF needs long response cycles and independent PUF components, leading to increased power consumption and area overhead. STT-mCell has emerged as a promising spintronic device to be used in logic circuit design with high energy efficiency. However, it is challenging to guarantee the security of the STT-mCell based circuit. In this work, we propose a novel STT-mCell Delay based PUF design (SD-PUF) and exploit the manufacturing process variation (PV) of STTmCell. We introduce a new methodology to select appropriate logic gates in the all-spin chip to generate an identification signature. Finally, a masking scheme is applied for signature improvement. The experimental results show that the uniqueness of the signature is 49.61% and the SD-PUF has area benefits over other designs.

Original language	English
Title of host publication	2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	165-168
Number of pages	4
ISBN (Electronic)	9781665439169
DOIs	https://doi.org/10.1109/APCCAS51387.2021.9687714
State	Published - 2021
Event	2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021 - Penang, Malaysia Duration: 22 Nov 2021 → 26 Nov 2021

Publication series

Name	2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021

Conference

Conference	2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021
Country/Territory	Malaysia
City	Penang
Period	22/11/21 → 26/11/21

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Hardware security
logic gate delay
physical unclonable function (PUF)
signature improvement
spintronics

Access to Document

10.1109/APCCAS51387.2021.9687714

Cite this

Xu, K. W., Zhang, D. R., & Cheng, Y. Q. (2021). SD-PUF: An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits. In 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021 (pp. 165-168). (2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS51387.2021.9687714

Xu, K. W. ; Zhang, D. R. ; Cheng, Y. Q. / SD-PUF : An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits. 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021. Institute of Electrical and Electronics Engineers Inc., 2021. pp. 165-168 (2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021).

@inproceedings{2a8cacd235a340daa33d43b9f3ed6540,

title = "SD-PUF: An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits",

abstract = "As the hardware security gets more and more attentions, Physically Unclonable Function (PUF) has been proposed to provide chip authentication and Intellectual Property protection effectively. The traditional PUF needs long response cycles and independent PUF components, leading to increased power consumption and area overhead. STT-mCell has emerged as a promising spintronic device to be used in logic circuit design with high energy efficiency. However, it is challenging to guarantee the security of the STT-mCell based circuit. In this work, we propose a novel STT-mCell Delay based PUF design (SD-PUF) and exploit the manufacturing process variation (PV) of STTmCell. We introduce a new methodology to select appropriate logic gates in the all-spin chip to generate an identification signature. Finally, a masking scheme is applied for signature improvement. The experimental results show that the uniqueness of the signature is 49.61\% and the SD-PUF has area benefits over other designs.",

keywords = "Hardware security, logic gate delay, physical unclonable function (PUF), signature improvement, spintronics",

author = "Xu, \{K. W.\} and Zhang, \{D. R.\} and Cheng, \{Y. Q.\}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021 ; Conference date: 22-11-2021 Through 26-11-2021",

year = "2021",

doi = "10.1109/APCCAS51387.2021.9687714",

language = "英语",

series = "2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "165--168",

booktitle = "2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021",

address = "美国",

}

Xu, KW, Zhang, DR & Cheng, YQ 2021, SD-PUF: An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits. in 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021. 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021, Institute of Electrical and Electronics Engineers Inc., pp. 165-168, 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021, Penang, Malaysia, 22/11/21. https://doi.org/10.1109/APCCAS51387.2021.9687714

SD-PUF: An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits. / Xu, K. W.; Zhang, D. R.; Cheng, Y. Q.
2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 165-168 (2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - SD-PUF

T2 - 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021

AU - Xu, K. W.

AU - Zhang, D. R.

AU - Cheng, Y. Q.

PY - 2021

Y1 - 2021

N2 - As the hardware security gets more and more attentions, Physically Unclonable Function (PUF) has been proposed to provide chip authentication and Intellectual Property protection effectively. The traditional PUF needs long response cycles and independent PUF components, leading to increased power consumption and area overhead. STT-mCell has emerged as a promising spintronic device to be used in logic circuit design with high energy efficiency. However, it is challenging to guarantee the security of the STT-mCell based circuit. In this work, we propose a novel STT-mCell Delay based PUF design (SD-PUF) and exploit the manufacturing process variation (PV) of STTmCell. We introduce a new methodology to select appropriate logic gates in the all-spin chip to generate an identification signature. Finally, a masking scheme is applied for signature improvement. The experimental results show that the uniqueness of the signature is 49.61% and the SD-PUF has area benefits over other designs.

AB - As the hardware security gets more and more attentions, Physically Unclonable Function (PUF) has been proposed to provide chip authentication and Intellectual Property protection effectively. The traditional PUF needs long response cycles and independent PUF components, leading to increased power consumption and area overhead. STT-mCell has emerged as a promising spintronic device to be used in logic circuit design with high energy efficiency. However, it is challenging to guarantee the security of the STT-mCell based circuit. In this work, we propose a novel STT-mCell Delay based PUF design (SD-PUF) and exploit the manufacturing process variation (PV) of STTmCell. We introduce a new methodology to select appropriate logic gates in the all-spin chip to generate an identification signature. Finally, a masking scheme is applied for signature improvement. The experimental results show that the uniqueness of the signature is 49.61% and the SD-PUF has area benefits over other designs.

KW - Hardware security

KW - logic gate delay

KW - physical unclonable function (PUF)

KW - signature improvement

KW - spintronics

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U2 - 10.1109/APCCAS51387.2021.9687714

DO - 10.1109/APCCAS51387.2021.9687714

M3 - 会议稿件

AN - SCOPUS:85126683451

T3 - 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021

SP - 165

EP - 168

BT - 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 22 November 2021 through 26 November 2021

ER -

Xu KW, Zhang DR, Cheng YQ. SD-PUF: An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits. In 2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 165-168. (2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021). doi: 10.1109/APCCAS51387.2021.9687714

SD-PUF: An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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