SACIM: A Synapse-inspired Asynchronous CIM with Discharging Feedback, Dynamic Delay and Parallelism Extension for CNN Inference

Tingran Chen; Xiao Ya Wang; Yuxuan Ran; Kaiying Yang; Yi Zhao; Kexun Cheng; Chen Li; He Zhang; Xueyan Wang; Biao Pan

doi:10.1109/TCSII.2026.3693271

SACIM: A Synapse-inspired Asynchronous CIM with Discharging Feedback, Dynamic Delay and Parallelism Extension for CNN Inference

Tingran Chen
, Xiao Ya Wang
, Yuxuan Ran
, Kaiying Yang
, Yi Zhao
, Kexun Cheng
, Chen Li
, He Zhang
, Xueyan Wang
, Biao Pan^*

^*Corresponding author for this work

School of Integrated Circuit Science and Engineering

Beihang University
University of Science and Technology Beijing

Research output: Contribution to journal › Article › peer-review

Abstract

This brief presents a charge-domain analog compute-in-memory (ACIM) architecture, the Synapse-inspired Asynchronous CIM (SACIM), which addresses key challenges in generality, latency, and parallelism. The architecture includes three structures: a Non-Differential Decoupled (NDDC) bit-cell array for implementing negative signed weights; a Clock-free Asynchronous Controller (CFAC) to dynamically shorten latency; and an asynchronous Pulse-based Analog-to-Digital Converter (PADC) circuit with an NDDC coordination mechanism for parallelism extension. Fabricated in 40nm CMOS, the prototype achieves a peak energy efficiency of 655.78 TOPS/W and a throughput of 1180.4 GOPS, with 5.1 μW static power in a 99,280 μm² area.

Original language	English
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
DOIs	https://doi.org/10.1109/TCSII.2026.3693271
State	Accepted/In press - 2026

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Analog Computing-in-Memory
charging feedback
dynamic delay
parallelism extension
signed weight

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10.1109/TCSII.2026.3693271

Cite this

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title = "SACIM: A Synapse-inspired Asynchronous CIM with Discharging Feedback, Dynamic Delay and Parallelism Extension for CNN Inference",

abstract = "This brief presents a charge-domain analog compute-in-memory (ACIM) architecture, the Synapse-inspired Asynchronous CIM (SACIM), which addresses key challenges in generality, latency, and parallelism. The architecture includes three structures: a Non-Differential Decoupled (NDDC) bit-cell array for implementing negative signed weights; a Clock-free Asynchronous Controller (CFAC) to dynamically shorten latency; and an asynchronous Pulse-based Analog-to-Digital Converter (PADC) circuit with an NDDC coordination mechanism for parallelism extension. Fabricated in 40nm CMOS, the prototype achieves a peak energy efficiency of 655.78 TOPS/W and a throughput of 1180.4 GOPS, with 5.1 μW static power in a 99,280 μm2 area.",

keywords = "Analog Computing-in-Memory, charging feedback, dynamic delay, parallelism extension, signed weight",

author = "Tingran Chen and Wang, \{Xiao Ya\} and Yuxuan Ran and Kaiying Yang and Yi Zhao and Kexun Cheng and Chen Li and He Zhang and Xueyan Wang and Biao Pan",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2026",

doi = "10.1109/TCSII.2026.3693271",

language = "英语",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T2 - A Synapse-inspired Asynchronous CIM with Discharging Feedback, Dynamic Delay and Parallelism Extension for CNN Inference

AU - Chen, Tingran

AU - Wang, Xiao Ya

AU - Ran, Yuxuan

AU - Yang, Kaiying

AU - Zhao, Yi

AU - Cheng, Kexun

AU - Li, Chen

AU - Zhang, He

AU - Wang, Xueyan

AU - Pan, Biao

PY - 2026

Y1 - 2026

N2 - This brief presents a charge-domain analog compute-in-memory (ACIM) architecture, the Synapse-inspired Asynchronous CIM (SACIM), which addresses key challenges in generality, latency, and parallelism. The architecture includes three structures: a Non-Differential Decoupled (NDDC) bit-cell array for implementing negative signed weights; a Clock-free Asynchronous Controller (CFAC) to dynamically shorten latency; and an asynchronous Pulse-based Analog-to-Digital Converter (PADC) circuit with an NDDC coordination mechanism for parallelism extension. Fabricated in 40nm CMOS, the prototype achieves a peak energy efficiency of 655.78 TOPS/W and a throughput of 1180.4 GOPS, with 5.1 μW static power in a 99,280 μm2 area.

AB - This brief presents a charge-domain analog compute-in-memory (ACIM) architecture, the Synapse-inspired Asynchronous CIM (SACIM), which addresses key challenges in generality, latency, and parallelism. The architecture includes three structures: a Non-Differential Decoupled (NDDC) bit-cell array for implementing negative signed weights; a Clock-free Asynchronous Controller (CFAC) to dynamically shorten latency; and an asynchronous Pulse-based Analog-to-Digital Converter (PADC) circuit with an NDDC coordination mechanism for parallelism extension. Fabricated in 40nm CMOS, the prototype achieves a peak energy efficiency of 655.78 TOPS/W and a throughput of 1180.4 GOPS, with 5.1 μW static power in a 99,280 μm2 area.

KW - Analog Computing-in-Memory

KW - charging feedback

KW - dynamic delay

KW - parallelism extension

KW - signed weight

UR - https://www.scopus.com/pages/publications/105039263859

U2 - 10.1109/TCSII.2026.3693271

DO - 10.1109/TCSII.2026.3693271

M3 - 文章

AN - SCOPUS:105039263859

SN - 1549-7747

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

ER -

SACIM: A Synapse-inspired Asynchronous CIM with Discharging Feedback, Dynamic Delay and Parallelism Extension for CNN Inference

Abstract

UN SDGs

Keywords

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