Research on carrier phase tracking error in ultra-tightly coupled GPS/INS integration

The design of carrier phase lock loop (PLL) is a key technology in the design of GPS receiver. The main error sources of PLL include phase jitter and dynamic stress error. With the increase of receiver platform dynamic, the larger dynamic stress error will lead to the loop loss lock. In order to adapt to the dynamic environment, the receiver usually use ultra-tightly coupled (UTC) GPS/INS integration with INS aided PLL tracking loops. Due to the aided information which the integration system provided may not be completely accurate, the tracking loop can reduce the dynamic stress error and will also introduce other measurement error sources. The PLL tracking error based on the INS estimation Doppler error was deduced in detail and two specific formulas were obtained. The simulations results showed that the PLL tracking error analysis were accurate on UTC system, which could provide reference for the optimal design PLL loop parameters.