RAP-CIM: Reliable Time Accumulation and Efficient Pipeline Computing in Memory with Spintronics for Neural Networks

Spintronic memories are considered one of the most promising memories to implement computing in memory (CIM) because of their inherent advantages of computing capability, non-volatility, high speed and endurance. However, they are less energy efficient to perform multiply-and- accumulate (MAC) operations due to their low tunnel magnetoresistance ratio (TMR) and complex logic scheduling operations. In this work, we propose a reliable time accumulation and efficient pipeline CIM (RAP-CIM) using spintronic memory to support MAC operation in neural networks. First, we propose a time accumulation structure based on time-domain converter and segmented bit-line technology to implement MAC operation by reading 1-bit from each bit-cell group on a column. Second, a pipeline computation structure for multicycle MAC operation is proposed to reduce computing delay. Finally, we construct a 2 Kb RAP-CIM architecture and evaluate its advantages for performing neural networks. Simulation results show the proposed RAP-CIM architecture realizes 119.7 TOPS/W and 31.5 TOPS/W for 4-bit and 8-bit MAC operations, respectively, while achieving high reliability.