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Random interface trap induced fluctuation in 22nm high-k/metal gate junctionless and inversion-mode FinFETs

  • Yijiao Wang
  • , Kangliang Wei
  • , Xiaoyan Liu
  • , Gang Du
  • , Jinfeng Kang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The impact of random interface trap (RIT) on the junctionless MOSFET (JL-FET) is investigated. Both acceptor-like and donor-like interface traps are considered to 22nm high-k metal gate (HKMG) junctionless structure and traditional inversion-mode FinFET. Fluctuations in threshold voltage, on current, leakage current, drain induced barrier lowering and subthreshold swing are analyzed. The results show that the position effect and type of interface traps (ITs) can induce different fluctuation for JL-FET and FinFET.

Original languageEnglish
Title of host publication2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
DOIs
StatePublished - 2013
Externally publishedYes
Event2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 - Hsinchu, Taiwan, Province of China
Duration: 22 Apr 201324 Apr 2013

Publication series

Name2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013

Conference

Conference2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
Country/TerritoryTaiwan, Province of China
CityHsinchu
Period22/04/1324/04/13

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