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Processing-in-Memory Enabled Graphics Processors for 3D Rendering

  • Chenhao Xie
  • , Shuaiwen Leon Song
  • , Jing Wang*
  • , Weigong Zhang
  • , Xin Fu
  • *Corresponding author for this work
  • University of Houston
  • Pacific Northwest National Laboratory
  • Capital Normal University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The performance of 3D rendering of GraphicsProcessing Unit that converts 3D vector stream into 2D framewith 3D image effects significantly impacts users gamingexperience on modern computer systems. Due to its hightexture throughput requirement, main memory bandwidthbecomes a critical obstacle for improving the overall renderingperformance. 3D-stacked memory systems such as HybridMemory Cube provide opportunities to significantly overcomethe memory wall by directly connecting logic controllers toDRAM dies. Although recent works have shown promisingimprovement in performance by utilizing HMC to acceleratespecial-purpose applications, a critical challenge of how toeffectively leverage its high internal bandwidth and computingcapability in GPU for 3D rendering remains unresolved. Basedon the observation that texel fetches greatly impact off-chipmemory traffic, we propose two architectural designs to enableProcessing-In-Memory based GPU for efficient 3D rendering. Additionally, we employ camera angles of pixels to controlthe performance-quality tradeoff of 3D rendering. Extensiveevaluation across several real-world games demonstrates thatour design can significantly improve the performance of texturefiltering and 3D rendering by an average of 3.97X (up to 6.4X) and 43% (up to 65%) respectively, over the baseline GPU. Meanwhile, our design provides considerable memory trafficand energy reduction without sacrificing rendering quality.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017
PublisherIEEE Computer Society
Pages637-648
Number of pages12
ISBN (Electronic)9781509049851
DOIs
StatePublished - 5 May 2017
Externally publishedYes
Event23rd IEEE Symposium on High Performance Computer Architecture, HPCA 2017 - Austin, United States
Duration: 4 Feb 20178 Feb 2017

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Conference

Conference23rd IEEE Symposium on High Performance Computer Architecture, HPCA 2017
Country/TerritoryUnited States
CityAustin
Period4/02/178/02/17

Keywords

  • 3D Rendering
  • 3D-Stacked Memory
  • Approximate Computing
  • GPU
  • Processing-In-Memory

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