Probabilistic modeling during power estimation for mixed polarity reed-muller logic circuits

Expressing logic functions in terms of Reed-Muller expansions is preferred in some communication circuits for its certain advantages like lower power dissipation. This paper presents a power estimation model for Mixed Polarity Reed-Muller (MPRM) logic circuits from a probabilistic point of view. It is mainly used in combinational circuits under the zero-delay hypothesis. A key feature of this technique is that it provides an accurate and efficient way to handle temporal signal correlations during estimation of average power by using lag-one Markov chains. Besides, an ordered binary-decision diagram (OBDD) based procedure is used to propagate the temporal correlations from the primary inputs throughout the network. This model has been evaluated in the C language and a comparative analysis has been presented for many benchmark circuits. The results show that this model gives very good accuracy and does well in low power design for MPRM logic circuits.