Pipeline-Optimized FPGA Implementation of BCH-LDPC Concatenated Codec Based on DVB-S2 Standard

This paper presents a high-performance BCH-LDPC concatenated forward error correction (FEC) system under the DVB-S2 standard, with hardware implementation on FPGA. For the BCH encoder, a four-bit parallel circular shift register architecture was designed and implemented based on theoretical derivation, ensuring full compatibility with all generator polynomials specified in the standard. Furthermore, an enhanced FiBM (Further-optimized Inverse-free Berlekamp-Massey) algorithm, derived from the RiBM (Reformulated Inverse-Free BM) algorithm, was adopted for error locator polynomial computation. By optimizing the iterative structure, the proposed algorithm effectively reduces the critical path delay, thereby supporting high-speed decoding. For the LDPC decoder, a pipelined architecture based on the layered Min-Sum algorithm was developed. By systematically analyzing the structural properties of the DVB-S2 parity-check matrix, the layer scheduling and pipeline optimization strategy for check nodes were redesigned, which substantially reduces pipeline stalls and decoding latency. Experimental results demonstrate that the proposed FPGA implementation significantly improves system throughput.