TY - GEN
T1 - PDS
T2 - 53rd Annual ACM IEEE Design Automation Conference, DAC 2016
AU - Kang, Wang
AU - Pang, Tingting
AU - Wu, Bi
AU - Lv, Weifeng
AU - Zhang, Youguang
AU - Sun, Guanyu
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2016 ACM.
PY - 2016/6/5
Y1 - 2016/6/5
N2 - STT-MRAM has been considered as one of the most promising nonvolatile memory candidates in the next-generation of computer architecture. However, the read reliability and dynamic write power concerns greatly hinder its practical application. In this paper, we propose a synergistic solution, namely pseudo-differential sensing (PDS), to jointly address these two concerns. Three techniques, including cell cluster, asymmetric sensing amplifier (ASA) and self-error-detection-correction (SEDC), are proposed to implement the PDS concept. Our experimental results show that the PDS scheme with the 3T3MTJ cell cluster can reduce the area (∼21.7%) and write power (∼25.6%) of the differential sensing (DS) scheme while improve the read reliability (read margin, ∼35.6%) of the typical sensing (TS) scheme for a 16 Mbit cache. Furthermore, the PDS scheme with the 1T3MTJ cell cluster can outperform both the TS and DS schemes in terms of area (∼40.0%, ∼66.1%), read latency (∼16.6%, ∼32.1%), read power (∼16.7%, ∼37.1%), write latency (∼5.4%, 16.3%) and write power (∼18.6%, ∼43.4%).
AB - STT-MRAM has been considered as one of the most promising nonvolatile memory candidates in the next-generation of computer architecture. However, the read reliability and dynamic write power concerns greatly hinder its practical application. In this paper, we propose a synergistic solution, namely pseudo-differential sensing (PDS), to jointly address these two concerns. Three techniques, including cell cluster, asymmetric sensing amplifier (ASA) and self-error-detection-correction (SEDC), are proposed to implement the PDS concept. Our experimental results show that the PDS scheme with the 3T3MTJ cell cluster can reduce the area (∼21.7%) and write power (∼25.6%) of the differential sensing (DS) scheme while improve the read reliability (read margin, ∼35.6%) of the typical sensing (TS) scheme for a 16 Mbit cache. Furthermore, the PDS scheme with the 1T3MTJ cell cluster can outperform both the TS and DS schemes in terms of area (∼40.0%, ∼66.1%), read latency (∼16.6%, ∼32.1%), read power (∼16.7%, ∼37.1%), write latency (∼5.4%, 16.3%) and write power (∼18.6%, ∼43.4%).
KW - Asymmetric sensing
KW - Error detection and correction
KW - Reliability
KW - STT-MRAM
KW - Write power
UR - https://www.scopus.com/pages/publications/84977117283
U2 - 10.1145/2897937.2898058
DO - 10.1145/2897937.2898058
M3 - 会议稿件
AN - SCOPUS:84977117283
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 53rd Annual Design Automation Conference, DAC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 5 June 2016 through 9 June 2016
ER -