TY - GEN
T1 - Parallelized key expansion algorithm for advanced encryption standard
AU - Murtaza, Abid
AU - Pirzada, Syed Jahanzeb Hussain
AU - Hasan, M. Nomam
AU - Xu, Tongge
AU - Jianwei, Liu
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - Advance Encryption Standard (AES) is an algorithm widely used for encryption, authentication, authenticated encryption as well as in security protocols for providing security services in many modern-day applications. The primary reasons for the extensive use of AES are its stronger security and faster speed than its competitors. In the AES algorithm, different keys derived from the main key are used in encryption rounds, to provide strength to the security of the algorithm. However, in standard AES key expansion algorithm, the sub-keys are derived sequentially, that is one after other. This dependence on the previous sub-key has two problems. Firstly, the key generation cannot be parallelized, secondly, if any single sub-key is known to the attacker, all the other sub-keys, including master key, can be extracted. Also, Differential Power Analysis attack is known effective on standard AES key schedule. In this paper, we proposed a new key parallelized expansion algorithm for AES. The proposed algorithm removes the dependence on other sub-keys to provide faster speed and enhanced security. The proposed algorithm has been implemented in MATLAB software and on FPGA. The results of implementation validate that the computational efficiency of the proposed algorithm is superior to standard AES Key expansion.
AB - Advance Encryption Standard (AES) is an algorithm widely used for encryption, authentication, authenticated encryption as well as in security protocols for providing security services in many modern-day applications. The primary reasons for the extensive use of AES are its stronger security and faster speed than its competitors. In the AES algorithm, different keys derived from the main key are used in encryption rounds, to provide strength to the security of the algorithm. However, in standard AES key expansion algorithm, the sub-keys are derived sequentially, that is one after other. This dependence on the previous sub-key has two problems. Firstly, the key generation cannot be parallelized, secondly, if any single sub-key is known to the attacker, all the other sub-keys, including master key, can be extracted. Also, Differential Power Analysis attack is known effective on standard AES key schedule. In this paper, we proposed a new key parallelized expansion algorithm for AES. The proposed algorithm removes the dependence on other sub-keys to provide faster speed and enhanced security. The proposed algorithm has been implemented in MATLAB software and on FPGA. The results of implementation validate that the computational efficiency of the proposed algorithm is superior to standard AES Key expansion.
KW - Advance encryption standard (AES)
KW - FPGA
KW - Information security
KW - Key expansion
KW - Satellite communication
UR - https://www.scopus.com/pages/publications/85082872995
U2 - 10.1109/ICSESS47205.2019.9040825
DO - 10.1109/ICSESS47205.2019.9040825
M3 - 会议稿件
AN - SCOPUS:85082872995
T3 - Proceedings of the IEEE International Conference on Software Engineering and Service Sciences, ICSESS
SP - 609
EP - 612
BT - Proceedings of 2019 IEEE 10th International Conference on Software Engineering and Service Science, ICSESS 2019
A2 - Li, Wenzheng
A2 - Babu, M. Surendra Prasad
PB - IEEE Computer Society
T2 - 10th IEEE International Conference on Software Engineering and Service Science, ICSESS 2019
Y2 - 18 October 2019 through 20 October 2019
ER -