PADCIM: A 1966.9-TOPS/W 2.09%-RMSE Probabilistic Approximate Dynamic-Logic Based Digital Computing-in-Memory Macro in 40nm

Wente Yi; Zhenyu Xue; Tianshuo Bai; Lehao Tan; Han Zhang; Jingcheng Gu; Jintao Mo; Wenjia Wang; Biao Pan; Weisheng Zhao

doi:10.1109/ESSERC66193.2025.11214086

PADCIM: A 1966.9-TOPS/W 2.09%-RMSE Probabilistic Approximate Dynamic-Logic Based Digital Computing-in-Memory Macro in 40nm

Wente Yi
, Zhenyu Xue
, Tianshuo Bai
, Lehao Tan
, Han Zhang
, Jingcheng Gu
, Jintao Mo
, Wenjia Wang
, Biao Pan^*
, Weisheng Zhao

^*Corresponding author for this work

School of Integrated Circuit Science and Engineering

Beihang University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This work presents a 1966.9-TOPS/W 2.09%-RMSE digital computing-in-memory (CIM) macro named PADCIM. It has three key features: 1) Probabilistic approximate adder tree (PAAT) coupled with delay clock chain, achieve high energy efficiency and low RMSE while resolving slope deviation. 2) Full dynamic-logic computing circuits (FDCC) combined with NP-Domino cascading, reduce chip power and area. 3) XOR-based multi-bit computation scheme (XMCS) integrated with bias-error compensation, enable accurate binary and multi-bit computations. Fabricated in 40 nm technology, PADCIM demonstrates 1.12 × higher energy efficiency and 1.92 × lower RMSE than the SOTA ADCIM. It further achieves up to 1.70 × higher energy efficiency over 28 nm / 12 nm-nodes chips, while delivering 87.56% (1b/1b) and 91.19% (4b/1b) inference accuracy on CIFAR-10.

Original language	English
Title of host publication	Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
Publisher	IEEE Computer Society
Pages	429-432
Number of pages	4
ISBN (Electronic)	9798331525392
DOIs	https://doi.org/10.1109/ESSERC66193.2025.11214086
State	Published - 2025
Event	51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 - Munich, Germany Duration: 8 Sep 2025 → 11 Sep 2025

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
Country/Territory	Germany
City	Munich
Period	8/09/25 → 11/09/25

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Digital computing-in-memory
full dynamic-logic
multi-bit computation
probabilistic approximate

Access to Document

10.1109/ESSERC66193.2025.11214086

Cite this

Yi, W., Xue, Z., Bai, T., Tan, L., Zhang, H., Gu, J., Mo, J., Wang, W., Pan, B., & Zhao, W. (2025). PADCIM: A 1966.9-TOPS/W 2.09%-RMSE Probabilistic Approximate Dynamic-Logic Based Digital Computing-in-Memory Macro in 40nm. In Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 (pp. 429-432). (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSERC66193.2025.11214086

@inproceedings{6c9202262a994f17981484c956a2393f,

title = "PADCIM: A 1966.9-TOPS/W 2.09\%-RMSE Probabilistic Approximate Dynamic-Logic Based Digital Computing-in-Memory Macro in 40nm",

abstract = "This work presents a 1966.9-TOPS/W 2.09\%-RMSE digital computing-in-memory (CIM) macro named PADCIM. It has three key features: 1) Probabilistic approximate adder tree (PAAT) coupled with delay clock chain, achieve high energy efficiency and low RMSE while resolving slope deviation. 2) Full dynamic-logic computing circuits (FDCC) combined with NP-Domino cascading, reduce chip power and area. 3) XOR-based multi-bit computation scheme (XMCS) integrated with bias-error compensation, enable accurate binary and multi-bit computations. Fabricated in 40 nm technology, PADCIM demonstrates 1.12 × higher energy efficiency and 1.92 × lower RMSE than the SOTA ADCIM. It further achieves up to 1.70 × higher energy efficiency over 28 nm / 12 nm-nodes chips, while delivering 87.56\% (1b/1b) and 91.19\% (4b/1b) inference accuracy on CIFAR-10.",

keywords = "Digital computing-in-memory, full dynamic-logic, multi-bit computation, probabilistic approximate",

author = "Wente Yi and Zhenyu Xue and Tianshuo Bai and Lehao Tan and Han Zhang and Jingcheng Gu and Jintao Mo and Wenjia Wang and Biao Pan and Weisheng Zhao",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 ; Conference date: 08-09-2025 Through 11-09-2025",

year = "2025",

doi = "10.1109/ESSERC66193.2025.11214086",

language = "英语",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

pages = "429--432",

booktitle = "Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025",

address = "美国",

}

Yi, W, Xue, Z, Bai, T, Tan, L, Zhang, H, Gu, J, Mo, J, Wang, W, Pan, B & Zhao, W 2025, PADCIM: A 1966.9-TOPS/W 2.09%-RMSE Probabilistic Approximate Dynamic-Logic Based Digital Computing-in-Memory Macro in 40nm. in Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. European Solid-State Circuits Conference, IEEE Computer Society, pp. 429-432, 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025, Munich, Germany, 8/09/25. https://doi.org/10.1109/ESSERC66193.2025.11214086

PADCIM: A 1966.9-TOPS/W 2.09%-RMSE Probabilistic Approximate Dynamic-Logic Based Digital Computing-in-Memory Macro in 40nm. / Yi, Wente; Xue, Zhenyu; Bai, Tianshuo et al.
Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society, 2025. p. 429-432 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - PADCIM

T2 - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025

AU - Yi, Wente

AU - Xue, Zhenyu

AU - Bai, Tianshuo

AU - Tan, Lehao

AU - Zhang, Han

AU - Gu, Jingcheng

AU - Mo, Jintao

AU - Wang, Wenjia

AU - Pan, Biao

AU - Zhao, Weisheng

PY - 2025

Y1 - 2025

N2 - This work presents a 1966.9-TOPS/W 2.09%-RMSE digital computing-in-memory (CIM) macro named PADCIM. It has three key features: 1) Probabilistic approximate adder tree (PAAT) coupled with delay clock chain, achieve high energy efficiency and low RMSE while resolving slope deviation. 2) Full dynamic-logic computing circuits (FDCC) combined with NP-Domino cascading, reduce chip power and area. 3) XOR-based multi-bit computation scheme (XMCS) integrated with bias-error compensation, enable accurate binary and multi-bit computations. Fabricated in 40 nm technology, PADCIM demonstrates 1.12 × higher energy efficiency and 1.92 × lower RMSE than the SOTA ADCIM. It further achieves up to 1.70 × higher energy efficiency over 28 nm / 12 nm-nodes chips, while delivering 87.56% (1b/1b) and 91.19% (4b/1b) inference accuracy on CIFAR-10.

AB - This work presents a 1966.9-TOPS/W 2.09%-RMSE digital computing-in-memory (CIM) macro named PADCIM. It has three key features: 1) Probabilistic approximate adder tree (PAAT) coupled with delay clock chain, achieve high energy efficiency and low RMSE while resolving slope deviation. 2) Full dynamic-logic computing circuits (FDCC) combined with NP-Domino cascading, reduce chip power and area. 3) XOR-based multi-bit computation scheme (XMCS) integrated with bias-error compensation, enable accurate binary and multi-bit computations. Fabricated in 40 nm technology, PADCIM demonstrates 1.12 × higher energy efficiency and 1.92 × lower RMSE than the SOTA ADCIM. It further achieves up to 1.70 × higher energy efficiency over 28 nm / 12 nm-nodes chips, while delivering 87.56% (1b/1b) and 91.19% (4b/1b) inference accuracy on CIFAR-10.

KW - Digital computing-in-memory

KW - full dynamic-logic

KW - multi-bit computation

KW - probabilistic approximate

UR - https://www.scopus.com/pages/publications/105024541326

U2 - 10.1109/ESSERC66193.2025.11214086

DO - 10.1109/ESSERC66193.2025.11214086

M3 - 会议稿件

AN - SCOPUS:105024541326

T3 - European Solid-State Circuits Conference

SP - 429

EP - 432

BT - Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025

PB - IEEE Computer Society

Y2 - 8 September 2025 through 11 September 2025

ER -

Yi W, Xue Z, Bai T, Tan L, Zhang H, Gu J et al. PADCIM: A 1966.9-TOPS/W 2.09%-RMSE Probabilistic Approximate Dynamic-Logic Based Digital Computing-in-Memory Macro in 40nm. In Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society. 2025. p. 429-432. (European Solid-State Circuits Conference). doi: 10.1109/ESSERC66193.2025.11214086

PADCIM: A 1966.9-TOPS/W 2.09%-RMSE Probabilistic Approximate Dynamic-Logic Based Digital Computing-in-Memory Macro in 40nm

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

Other files and links

Fingerprint

Cite this