TY - GEN
T1 - OpenCGRA
T2 - 32nd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2021
AU - Tan, Cheng
AU - Agostini, Nicolas Bohm
AU - Zhang, Jeff
AU - Minutoli, Marco
AU - Castellana, Vito Giovanni
AU - Xie, Chenhao
AU - Geng, Tong
AU - Li, Ang
AU - Barker, Kevin
AU - Tumeo, Antonino
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/7
Y1 - 2021/7
N2 - Reconfigurable architectures are today experiencing a renewed interest for their ability to provide specialization without sacrificing the capability to adapt to disparate workloads. Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) while offering increased hardware efficiency with respect to field-programmable gate arrays (FPGAs). This makes CGRAs a promising alternative to enable power-/area-efficient acceleration across different application domains. Unfortunately, specializing and implementing a CGRA for a specific application domain requires the exploration in a large design space (e.g., applying appropriate loop transformation on each application, specializing the reconfigurable processing elements of the CGRA, refining the network topology, deciding the size of the data memory, etc.) and involves enormous software/hardware engineering effort (e.g., modeling, testing, and evaluating the CGRA, map operations onto the CGRA, etc). In this paper, we discuss a hardware/software co-design framework* to automatically specialize and implement optimal CGRA designs given a set of applications of interest.
AB - Reconfigurable architectures are today experiencing a renewed interest for their ability to provide specialization without sacrificing the capability to adapt to disparate workloads. Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) while offering increased hardware efficiency with respect to field-programmable gate arrays (FPGAs). This makes CGRAs a promising alternative to enable power-/area-efficient acceleration across different application domains. Unfortunately, specializing and implementing a CGRA for a specific application domain requires the exploration in a large design space (e.g., applying appropriate loop transformation on each application, specializing the reconfigurable processing elements of the CGRA, refining the network topology, deciding the size of the data memory, etc.) and involves enormous software/hardware engineering effort (e.g., modeling, testing, and evaluating the CGRA, map operations onto the CGRA, etc). In this paper, we discuss a hardware/software co-design framework* to automatically specialize and implement optimal CGRA designs given a set of applications of interest.
UR - https://www.scopus.com/pages/publications/85114908404
U2 - 10.1109/ASAP52443.2021.00029
DO - 10.1109/ASAP52443.2021.00029
M3 - 会议稿件
AN - SCOPUS:85114908404
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 149
EP - 155
BT - Proceedings - 32nd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 7 July 2021 through 8 July 2021
ER -