Novel technique to planarize nano-sized high-k metal gate in fabrication of advanced CMOS devices

Here, we addressedthe “over-etching” problem, originated from the conventionalplanarization of the high-k metal gate in fabricating advanced complementary metal oxide semiconductor (CMOS) devices with nanoscale feature size (<30 nm). The novel planarization technique, compatible with the state-of-the-art integrated circuit fabrication technology, mainly included 3-steps: reactive ion etching, deposition of tetraethyl orthosilicate layerand chemical mechanical polishing (CMP). The impact of the planarization conditions on the surface and cross-sectional structures of the high-k metal gate was investigated with scanning electron microscopy for process optimization. The test results show that the newly-developed planarization method outperformed the conventional CMP, because it effectively planarized the high-k metal gate and significantly weakened the large-area corrosion/erosion of the gate's metal-layer. We suggest that the novel technique be of some technological interest in fabrication of high-k metal gate for the CMOS devices with feature size ≤22 nm.