Novel optimized implementation of CABAC hardware encoder

To improve the throughput of hardware architecture for CABAC (context-based adaptive binary arithmetic coder), the optimization methods based on dynamic properties of dataflow were adopted. By building the dataflow model of CABAC algorithm, four inevitable loops brought by hardware implementation were abstracted and isolated, and the potential bottle-neck loops were examined and optimized. For the context-loop, three assistant sub-loops with different iteration cycle were used to update the context variables needed by the data elements with different dependency-cycle. For the byte-package loop, a special kind of data elements was discriminated, which could simplify the circuit architecture and speed up the clock frequency. By building a dedicated fast by-pass channel for these special data elements, the throughput of byte-package loop was improved. Also benefiting from other basic optimization methods, the entire CABAC hardware architecture could achieve 309 MHz on FPGA (field-programmable gate array) platform and process one binary symbol per clock cycle.