Novel FPGA-based pipelined floating point FFT processor

Li Wei; Wang Jun

doi:10.1587/elex.7.268

Novel FPGA-based pipelined floating point FFT processor

Li Wei^*
, Wang Jun

^*Corresponding author for this work

School of Electronic and Information Engineering

Beihang University

Research output: Contribution to journal › Article › peer-review

Abstract

Two novel architectures for pipelined floating point fast Fourier transform on FPGA are presented. The new radix-2² two-path delay feedback (R2²TDF) architecture leads to 50% area saving for floating point complex adders compared with the radix-2² single-path delay feedback (R2²SDF) architecture. Besides a new hybrid archi- tecture is presented which mixes the R2²TDF and R2²TDF butterfly structures and is flexible and efficient for FPGA implementation.

Original language	English
Pages (from-to)	268-272
Number of pages	5
Journal	IEICE Electronics Express
Volume	7
Issue number	4
DOIs	https://doi.org/10.1587/elex.7.268
State	Published - 25 Feb 2010

Keywords

FFT
FPGA
Floating point
Pipelined

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10.1587/elex.7.268

Cite this

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abstract = "Two novel architectures for pipelined floating point fast Fourier transform on FPGA are presented. The new radix-22 two-path delay feedback (R22TDF) architecture leads to 50\% area saving for floating point complex adders compared with the radix-22 single-path delay feedback (R22SDF) architecture. Besides a new hybrid archi- tecture is presented which mixes the R22TDF and R22TDF butterfly structures and is flexible and efficient for FPGA implementation.",

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KW - Floating point

KW - Pipelined

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Novel FPGA-based pipelined floating point FFT processor

Abstract

Keywords

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