Non-volatile register based on hybrid spintronics/CMOS technology

Weisheng Zhao; Eric Belhaire; Claude Chappert; Virgile Javerliac; Pascale Mazoyer

doi:10.1109/ICSICT.2008.4735018

Non-volatile register based on hybrid spintronics/CMOS technology

Weisheng Zhao^*
, Eric Belhaire
, Claude Chappert
, Virgile Javerliac
, Pascale Mazoyer

^*Corresponding author for this work

CNRS
Université Paris-Saclay
Crocus Technology
STMicroelectronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, we present a non-volatile register based on hybrid Spintronics/CMOS technology, which can store securely and non-vocatively all the intermediate data in the logic circuits as FPGA and ASIC. The non-volatility of this register allows to power down the circuits keeping the data thereby reduce significantly the standby power and accelerate the chip re (boot) latency. Based on STMicroelectronics 90nm design kit and a complete MTJ Spice model for MRAM development, the delay propagation of this register is lower than 500ps. We propose also the solutions to overcome the high sensitivity issue for this non-volatile register.

Original language	English
Title of host publication	ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings
Pages	2136-2139
Number of pages	4
DOIs	https://doi.org/10.1109/ICSICT.2008.4735018
State	Published - 2008
Externally published	Yes
Event	2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 - Beijing, China Duration: 20 Oct 2008 → 23 Oct 2008

Publication series

Name	International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Conference

Conference	2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008
Country/Territory	China
City	Beijing
Period	20/10/08 → 23/10/08

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10.1109/ICSICT.2008.4735018

Cite this

Zhao, W., Belhaire, E., Chappert, C., Javerliac, V., & Mazoyer, P. (2008). Non-volatile register based on hybrid spintronics/CMOS technology. In ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings (pp. 2136-2139). Article 4735018 (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT). https://doi.org/10.1109/ICSICT.2008.4735018

@inproceedings{b60a6ed2f6da44968b96aa27c577df32,

title = "Non-volatile register based on hybrid spintronics/CMOS technology",

abstract = "In this paper, we present a non-volatile register based on hybrid Spintronics/CMOS technology, which can store securely and non-vocatively all the intermediate data in the logic circuits as FPGA and ASIC. The non-volatility of this register allows to power down the circuits keeping the data thereby reduce significantly the standby power and accelerate the chip re (boot) latency. Based on STMicroelectronics 90nm design kit and a complete MTJ Spice model for MRAM development, the delay propagation of this register is lower than 500ps. We propose also the solutions to overcome the high sensitivity issue for this non-volatile register.",

author = "Weisheng Zhao and Eric Belhaire and Claude Chappert and Virgile Javerliac and Pascale Mazoyer",

year = "2008",

doi = "10.1109/ICSICT.2008.4735018",

language = "英语",

isbn = "9781424421855",

series = "International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT",

pages = "2136--2139",

booktitle = "ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings",

note = "2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 ; Conference date: 20-10-2008 Through 23-10-2008",

}

Zhao, W, Belhaire, E, Chappert, C, Javerliac, V & Mazoyer, P 2008, Non-volatile register based on hybrid spintronics/CMOS technology. in ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings., 4735018, International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, pp. 2136-2139, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008, Beijing, China, 20/10/08. https://doi.org/10.1109/ICSICT.2008.4735018

Non-volatile register based on hybrid spintronics/CMOS technology. / Zhao, Weisheng; Belhaire, Eric; Chappert, Claude et al.
ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings. 2008. p. 2136-2139 4735018 (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Non-volatile register based on hybrid spintronics/CMOS technology

AU - Zhao, Weisheng

AU - Belhaire, Eric

AU - Chappert, Claude

AU - Javerliac, Virgile

AU - Mazoyer, Pascale

PY - 2008

Y1 - 2008

N2 - In this paper, we present a non-volatile register based on hybrid Spintronics/CMOS technology, which can store securely and non-vocatively all the intermediate data in the logic circuits as FPGA and ASIC. The non-volatility of this register allows to power down the circuits keeping the data thereby reduce significantly the standby power and accelerate the chip re (boot) latency. Based on STMicroelectronics 90nm design kit and a complete MTJ Spice model for MRAM development, the delay propagation of this register is lower than 500ps. We propose also the solutions to overcome the high sensitivity issue for this non-volatile register.

AB - In this paper, we present a non-volatile register based on hybrid Spintronics/CMOS technology, which can store securely and non-vocatively all the intermediate data in the logic circuits as FPGA and ASIC. The non-volatility of this register allows to power down the circuits keeping the data thereby reduce significantly the standby power and accelerate the chip re (boot) latency. Based on STMicroelectronics 90nm design kit and a complete MTJ Spice model for MRAM development, the delay propagation of this register is lower than 500ps. We propose also the solutions to overcome the high sensitivity issue for this non-volatile register.

UR - https://www.scopus.com/pages/publications/60649093531

U2 - 10.1109/ICSICT.2008.4735018

DO - 10.1109/ICSICT.2008.4735018

M3 - 会议稿件

AN - SCOPUS:60649093531

SN - 9781424421855

T3 - International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

SP - 2136

EP - 2139

BT - ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings

T2 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

Y2 - 20 October 2008 through 23 October 2008

ER -

Zhao W, Belhaire E, Chappert C, Javerliac V, Mazoyer P. Non-volatile register based on hybrid spintronics/CMOS technology. In ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings. 2008. p. 2136-2139. 4735018. (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT). doi: 10.1109/ICSICT.2008.4735018

Non-volatile register based on hybrid spintronics/CMOS technology

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