NeuC-CIM: A 1.3pJ/SOP Neuromorphic Charge-Domain Compute-in-Memory Macro for Spiking Neural Network

Haotian Fu; Hongzhao Zheng; Yue Zhou; Xianshan Wen; Yize Chen; Hongwei Ren; Xiaopeng Lin; Zhirui Zong; Lianbo Wu; Bojun Cheng

doi:10.23919/VLSITechnologyandCir65189.2025.11074927

NeuC-CIM: A 1.3pJ/SOP Neuromorphic Charge-Domain Compute-in-Memory Macro for Spiking Neural Network

Haotian Fu
, Hongzhao Zheng
, Yue Zhou
, Xianshan Wen
, Yize Chen
, Hongwei Ren
, Xiaopeng Lin
, Zhirui Zong
, Lianbo Wu^*
, Bojun Cheng^*

^*Corresponding author for this work

School of Integrated Circuit Science and Engineering

The Hong Kong University of Science and Technology (Guangzhou)
Beihang University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This work presents NeuC-CIM, an energy efficient neuromorphic compute-in-memory macro. The proposed multi-bit charge-domain synapse and the event-triggered spiking neuron enables efficient, DC-current free operation. Moreover, the capacity extension module and neuron cyclic calibration scheme are proposed to reduce the nonlinearity and mismatch-induced accuracy loss in analog synapse and neuron circuits. The effectiveness of NeuC-CIM is verified in silicon with various neuromorphic tasks, showing a state-of-the-art 1.3 pJ/SOP energy efficiency with comparable accuracy.

Original language	English
Title of host publication	2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863488151
DOIs	https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11074927
State	Published - 2025
Event	2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025 - Kyoto, Japan Duration: 8 Jun 2025 → 12 Jun 2025

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562
ISSN (Electronic)	2158-9682

Conference

Conference	2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025
Country/Territory	Japan
City	Kyoto
Period	8/06/25 → 12/06/25

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Charge-sharing
Compute-In-Memory
Neuromorphic Computing
Spiking neural networks

Access to Document

10.23919/VLSITechnologyandCir65189.2025.11074927

Cite this

Fu, H., Zheng, H., Zhou, Y., Wen, X., Chen, Y., Ren, H., Lin, X., Zong, Z., Wu, L., & Cheng, B. (2025). NeuC-CIM: A 1.3pJ/SOP Neuromorphic Charge-Domain Compute-in-Memory Macro for Spiking Neural Network. In 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025 (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11074927

@inproceedings{e9fd46b284e641098e2b15d939693e86,

title = "NeuC-CIM: A 1.3pJ/SOP Neuromorphic Charge-Domain Compute-in-Memory Macro for Spiking Neural Network",

abstract = "This work presents NeuC-CIM, an energy efficient neuromorphic compute-in-memory macro. The proposed multi-bit charge-domain synapse and the event-triggered spiking neuron enables efficient, DC-current free operation. Moreover, the capacity extension module and neuron cyclic calibration scheme are proposed to reduce the nonlinearity and mismatch-induced accuracy loss in analog synapse and neuron circuits. The effectiveness of NeuC-CIM is verified in silicon with various neuromorphic tasks, showing a state-of-the-art 1.3 pJ/SOP energy efficiency with comparable accuracy.",

keywords = "Charge-sharing, Compute-In-Memory, Neuromorphic Computing, Spiking neural networks",

author = "Haotian Fu and Hongzhao Zheng and Yue Zhou and Xianshan Wen and Yize Chen and Hongwei Ren and Xiaopeng Lin and Zhirui Zong and Lianbo Wu and Bojun Cheng",

note = "Publisher Copyright: {\textcopyright} 2025 JSAP.; 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025 ; Conference date: 08-06-2025 Through 12-06-2025",

year = "2025",

doi = "10.23919/VLSITechnologyandCir65189.2025.11074927",

language = "英语",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025",

address = "美国",

}

Fu, H, Zheng, H, Zhou, Y, Wen, X, Chen, Y, Ren, H, Lin, X, Zong, Z, Wu, L & Cheng, B 2025, NeuC-CIM: A 1.3pJ/SOP Neuromorphic Charge-Domain Compute-in-Memory Macro for Spiking Neural Network. in 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025. Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025, Kyoto, Japan, 8/06/25. https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11074927

NeuC-CIM: A 1.3pJ/SOP Neuromorphic Charge-Domain Compute-in-Memory Macro for Spiking Neural Network. / Fu, Haotian; Zheng, Hongzhao; Zhou, Yue et al.
2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025. Institute of Electrical and Electronics Engineers Inc., 2025. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - NeuC-CIM

T2 - 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025

AU - Fu, Haotian

AU - Zheng, Hongzhao

AU - Zhou, Yue

AU - Wen, Xianshan

AU - Chen, Yize

AU - Ren, Hongwei

AU - Lin, Xiaopeng

AU - Zong, Zhirui

AU - Wu, Lianbo

AU - Cheng, Bojun

PY - 2025

Y1 - 2025

N2 - This work presents NeuC-CIM, an energy efficient neuromorphic compute-in-memory macro. The proposed multi-bit charge-domain synapse and the event-triggered spiking neuron enables efficient, DC-current free operation. Moreover, the capacity extension module and neuron cyclic calibration scheme are proposed to reduce the nonlinearity and mismatch-induced accuracy loss in analog synapse and neuron circuits. The effectiveness of NeuC-CIM is verified in silicon with various neuromorphic tasks, showing a state-of-the-art 1.3 pJ/SOP energy efficiency with comparable accuracy.

AB - This work presents NeuC-CIM, an energy efficient neuromorphic compute-in-memory macro. The proposed multi-bit charge-domain synapse and the event-triggered spiking neuron enables efficient, DC-current free operation. Moreover, the capacity extension module and neuron cyclic calibration scheme are proposed to reduce the nonlinearity and mismatch-induced accuracy loss in analog synapse and neuron circuits. The effectiveness of NeuC-CIM is verified in silicon with various neuromorphic tasks, showing a state-of-the-art 1.3 pJ/SOP energy efficiency with comparable accuracy.

KW - Charge-sharing

KW - Compute-In-Memory

KW - Neuromorphic Computing

KW - Spiking neural networks

UR - https://www.scopus.com/pages/publications/105012226622

U2 - 10.23919/VLSITechnologyandCir65189.2025.11074927

DO - 10.23919/VLSITechnologyandCir65189.2025.11074927

M3 - 会议稿件

AN - SCOPUS:105012226622

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 8 June 2025 through 12 June 2025

ER -

Fu H, Zheng H, Zhou Y, Wen X, Chen Y, Ren H et al. NeuC-CIM: A 1.3pJ/SOP Neuromorphic Charge-Domain Compute-in-Memory Macro for Spiking Neural Network. In 2025 Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2025. Institute of Electrical and Electronics Engineers Inc. 2025. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSITechnologyandCir65189.2025.11074927

NeuC-CIM: A 1.3pJ/SOP Neuromorphic Charge-Domain Compute-in-Memory Macro for Spiking Neural Network

Abstract

Publication series

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UN SDGs

Keywords

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