Multi-Retention and Bit-Level Approximate STT-MRAM for High-Efficiency AI Applications

Magnetoresistive random-access memory (MRAM) is a strong alternative to dynamic random-access memory (DRAM) in the future main memory domain with its extremely low static power consumption and fast read/write speeds. However, existing designs fail to leverage the advantage of MRAM in the field of deep neural networks (DNNs), where data volumes are increasingly massive. In this paper, we propose a multi-retention MRAM architecture along with approximate computing (AC) based on spin-transfer torque MRAM (STT-MRAM) to improve write energy efficiency. Additionally, we put forward a fully pipelined read scheme to enhance read speed utilizing the standard array. Finally, we further optimize the approximation strategy through algorithms and conduct evaluation and validation on convolutional neural networks (CNN) and transformer-based models. The proposed architecture is evaluated using a 28 nm process combined with a SPICE model of the STT-MRAM. Simulation results indicate that the write energy consumption for activations using low data retention time is reduced by 79.8%, and the approximate strategy further reduces it by 28.3%, while the maximum model accuracy loss remains below 2.8%.