TY - GEN
T1 - Multi-context non-volatile content addressable memory using magnetic tunnel junctions
AU - Deng, Erya
AU - Anghel, Lorena
AU - Prenat, Guillaume
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2016 ACM.
PY - 2016/9/14
Y1 - 2016/9/14
N2 - As we are approaching the physical limits of the miniaturization of CMOS structures, the magnetic tunnel junction with spin transfer torque programing (STT-MTJ) are under intense investigation for power reduction for both memories and logic function implementations. In this paper, we present a novel design of non-volatile content addressable memory (NV-CAM) using STT-MTJs and logic-in-memory (LIM) architecture. In this NV-CAM, multiple memory cells share the same comparison circuit to provide area efficiency. A non-volatile switching circuit (NV-SC) has been developed for word line selection. If there is an occurrence of an unexpected power-off, search operation starts again from the stored word line instead of the beginning of the comparison sequence. Hence, the overall energy is further reduced. By using an industrial CMOS 28 nm design kit and a MTJ compact model, we validate the functionality of proposed NV-CAM and confirm its merits of high speed, low power consumption and low bit-cell cost.
AB - As we are approaching the physical limits of the miniaturization of CMOS structures, the magnetic tunnel junction with spin transfer torque programing (STT-MTJ) are under intense investigation for power reduction for both memories and logic function implementations. In this paper, we present a novel design of non-volatile content addressable memory (NV-CAM) using STT-MTJs and logic-in-memory (LIM) architecture. In this NV-CAM, multiple memory cells share the same comparison circuit to provide area efficiency. A non-volatile switching circuit (NV-SC) has been developed for word line selection. If there is an occurrence of an unexpected power-off, search operation starts again from the stored word line instead of the beginning of the comparison sequence. Hence, the overall energy is further reduced. By using an industrial CMOS 28 nm design kit and a MTJ compact model, we validate the functionality of proposed NV-CAM and confirm its merits of high speed, low power consumption and low bit-cell cost.
KW - Magnetic tunnel junction
KW - content addressable memory
KW - logic-in-memory
KW - multi-context
KW - non-volatile
UR - https://www.scopus.com/pages/publications/84992159467
U2 - 10.1145/2950067.2950106
DO - 10.1145/2950067.2950106
M3 - 会议稿件
AN - SCOPUS:84992159467
T3 - Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
SP - 103
EP - 108
BT - Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
PB - Presses Polytechniques Et Universitaires Romandes
T2 - 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
Y2 - 18 July 2016 through 20 July 2016
ER -