Modified potential well formed by Si/SiO2/TiN/TiO 2/SiO2/TaN for flash memory application

Gang Zhang; Chang Ho Ra; Hua Min Li; Tian Zi Shen; Byung Ki Cheong; Won Jong Yoo

doi:10.1109/TED.2010.2066200

Modified potential well formed by Si/SiO₂/TiN/TiO ₂/SiO₂/TaN for flash memory application

Gang Zhang^*
, Chang Ho Ra
, Hua Min Li
, Tian Zi Shen
, Byung Ki Cheong
, Won Jong Yoo

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

This paper proposes a modified engineered-potential-well (MW) for NAND flash memory application. The MW was formed by using a transitional SiO ₂/SiO_xN_y-TiO_xN_y tunnel barrier, a trap-rich TiO₂ trapping layer, and an abrupt SiO ₂ block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N₂ + O₂ thermal treatment, and the TiO₂ trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming (< μs) at low-voltage operation (710 MV/cm), good P/E endurance (10⁶P/E cycles), large threshold voltage window (Δ V_th = ∼6 V), as well as improved data retention at 125 °C.

Original language	English
Article number	5570944
Pages (from-to)	2794-2800
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	57
Issue number	11
DOIs	https://doi.org/10.1109/TED.2010.2066200
State	Published - Nov 2010
Externally published	Yes

Keywords

Flash memory
TiO trapping layer
modified engineered-potential- well (MW)

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10.1109/TED.2010.2066200

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@article{5641cb2a76c443a39617d0055afc6ac5,

title = "Modified potential well formed by Si/SiO2/TiN/TiO 2/SiO2/TaN for flash memory application",

abstract = "This paper proposes a modified engineered-potential-well (MW) for NAND flash memory application. The MW was formed by using a transitional SiO 2/SiOxNy-TiOxNy tunnel barrier, a trap-rich TiO2 trapping layer, and an abrupt SiO 2 block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N2 + O2 thermal treatment, and the TiO2 trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming (< μs) at low-voltage operation (710 MV/cm), good P/E endurance (106P/E cycles), large threshold voltage window (Δ Vth = ∼6 V), as well as improved data retention at 125 °C.",

keywords = "Flash memory, TiO trapping layer, modified engineered-potential- well (MW)",

author = "Gang Zhang and Ra, \{Chang Ho\} and Li, \{Hua Min\} and Shen, \{Tian Zi\} and Cheong, \{Byung Ki\} and Yoo, \{Won Jong\}",

year = "2010",

month = nov,

doi = "10.1109/TED.2010.2066200",

language = "英语",

volume = "57",

pages = "2794--2800",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

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TY - JOUR

T1 - Modified potential well formed by Si/SiO2/TiN/TiO 2/SiO2/TaN for flash memory application

AU - Zhang, Gang

AU - Ra, Chang Ho

AU - Li, Hua Min

AU - Shen, Tian Zi

AU - Cheong, Byung Ki

AU - Yoo, Won Jong

PY - 2010/11

Y1 - 2010/11

N2 - This paper proposes a modified engineered-potential-well (MW) for NAND flash memory application. The MW was formed by using a transitional SiO 2/SiOxNy-TiOxNy tunnel barrier, a trap-rich TiO2 trapping layer, and an abrupt SiO 2 block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N2 + O2 thermal treatment, and the TiO2 trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming (< μs) at low-voltage operation (710 MV/cm), good P/E endurance (106P/E cycles), large threshold voltage window (Δ Vth = ∼6 V), as well as improved data retention at 125 °C.

AB - This paper proposes a modified engineered-potential-well (MW) for NAND flash memory application. The MW was formed by using a transitional SiO 2/SiOxNy-TiOxNy tunnel barrier, a trap-rich TiO2 trapping layer, and an abrupt SiO 2 block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N2 + O2 thermal treatment, and the TiO2 trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming (< μs) at low-voltage operation (710 MV/cm), good P/E endurance (106P/E cycles), large threshold voltage window (Δ Vth = ∼6 V), as well as improved data retention at 125 °C.

KW - Flash memory

KW - TiO trapping layer

KW - modified engineered-potential- well (MW)

UR - https://www.scopus.com/pages/publications/78049318900

U2 - 10.1109/TED.2010.2066200

DO - 10.1109/TED.2010.2066200

M3 - 文章

AN - SCOPUS:78049318900

SN - 0018-9383

VL - 57

SP - 2794

EP - 2800

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 11

M1 - 5570944

ER -

Modified potential well formed by Si/SiO₂/TiN/TiO ₂/SiO₂/TaN for flash memory application

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Keywords

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