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Modeling of 6T-SRAM transistor failure and faults caused by injected noise in neural networkst

  • Zhiyuan Li
  • , Bo Sun
  • , Xiaoyan Xie
  • , Yue Sun
  • Guangdong University of Technology
  • Xiaomi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

By conducting failure simulations on the classic 6T-SRAM model across different transistor process nodes, the bit-flip behavior during read and write operations under failure conditions was observed. Based on the simulation results, a probabilistic model for the failure scenarios was established. This failure model was then applied to various neural networks by injecting different levels of noise. It was observed that the noise intensity exhibited a locally negative correlation with the prediction accuracy of the neural networks.

Original languageEnglish
Title of host publicationProceedings - 2025 26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2025
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350393002
DOIs
StatePublished - 2025
Externally publishedYes
Event26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2025 - Utrecht, Netherlands
Duration: 6 Apr 20259 Apr 2025

Publication series

NameProceedings - 2025 26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2025

Conference

Conference26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2025
Country/TerritoryNetherlands
CityUtrecht
Period6/04/259/04/25

Keywords

  • 6T-SRAM
  • bit flip
  • neural network
  • noise injection

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